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MPC5123YVY300BR 数据表(PDF) 34 Page - Freescale Semiconductor, Inc |
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MPC5123YVY300BR 数据表(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 86 page  MPC5121E/MPC5123 Data Sheet, Rev. 1 Electrical and Thermal Characteristics Freescale Semiconductor 34 Figure 10. DDR AC Test Load 3.3.6 PCI The PCI interface on the MPC5121e/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations. See the PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board, without any external buffers or other glue logic. Parameters apply at the package pins, not at expansion board edge connectors. The PCI_CLK is used as output clock, the MPC5121e/MPC5123 is a PCI host device only. Figure 11 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 22 summarizes the clock specifications. Figure 11. PCI CLK Waveform 2 Table 21. PCI CLK Specifications Sym Description 66 MHz1 1 In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz. 33 MHz Units SpecID Min2 2 Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 11. Max Min Max tcyc PCI CLK Cycle Time1,3 3 The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 15 30 30 — ns A6.1 thigh PCI CLK High Time 6 — 11 — ns A6.2 tlow PCI CLK Low Time 6 — 11 — ns A6.3 — PCI CLK Slew Rate2 1.5 4 1 4 V/ns A6.4 Output Z0 = 50 Ω RL = 50 Ω VDD_MEM_IO/2 tcyc PCI CLK tlow thigh 0.4Vcc 0.4Vcc, p-to-p 0.3Vcc 0.5Vcc 0.6Vcc 0.2Vcc (minimum) Preliminary |
类似零件编号 - MPC5123YVY300BR |
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类似说明 - MPC5123YVY300BR |
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