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ADP5588 数据表(PDF) 10 Page - Analog Devices |
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ADP5588 数据表(HTML) 10 Page - Analog Devices |
10 / 28 page ADP5588 Rev. A | Page 10 of 28 Table 13. GPI Event Number Assignments for Rows R0 R1 R2 R3 R4 R5 R6 is programmed as high, a high on that pin is considered active and meets the interrupt requirement. If the interrupt is pro- grammed as low, a low on that pin is considered active and meets the interrupt requirement. R7 97 98 99 100 101 102 103 104 Table 14. GPI Event Number Assignments for Columns C0 C1 C2 C3 C4 C5 C6 C7 C8 GPI data and interrupt status are reflected in the GPIO interrupt and data status registers (Register 0x11 through Register 0x16). Caution must be taken during software implementation because an interrupt may be set immediately after register settings. To prevent this, correct logic levels must be present at the GPIs, and the GPIO interrupt level must be set before GPIO interrupt enable or GPI event FIFO enable registers are set. Figure 8 shows the interrupt generation scheme, where Dx represents any one of the 18 GPIOs. C9 105 106 107 108 109 110 111 112 113 114 For a GPI that is set as active high, and is enabled in the key event table, the state machine adds an event to the event count and event table whenever that GPI goes high. If the GPI is set to active low, a transition from high to low is considered a press and is also added to the event count and event table. After the interrupt state is met, the state machine internally sets an interrupt for the opposite state programmed in the register to prevent polling for the released state, thereby saving current. After the released state is achieved, it is added to the event table. The press and release are still indicated by Bit 7 in the event register (Register 0x04 through Register 0x0D). The GPI events can also be used as unlocked sequences. Dx_IN REG. 0x23 THROUGH 0x25 Dx_IN_IEN Dx_IN_ISTAT REG. 0x11 THROUGH 0x13 READ TWICE TO CLEAR GPI_INT REG. 0x01 REG. 0x02 WRITE 1 TO CLEAR INT INTERRUPT CONDITION DECODE DRIVE Dx_ILVL REG. 0x26 THROUGH 0x28 AND When the GPI_EM_REGx bit in Register 0x20 through Register 0x22 is set, GPI events are not tracked when the keypad is locked. The GPIEM_CFG bit (Register 0x01, Bit 6) must be cleared for the GPI events to be tracked in the event counter and event table when the keypad is locked. Figure 8. GPIO Interrupt Generation GPI Events A column or row configured as a GPI can be programmed to be part of the key event table and therefore also capable of gener- ating a key event interrupt. A key event interrupt caused by a GPI follows the same process flow as a key event interrupt caused by a key press. GPIs configured as part of the key event table allow single key switches and other GPI interrupts to be monitored. As part of the event table, GPIs are represented by the decimal value 97 (0x61 or 1100001) through the decimal value 114 (0x72 or 1110010). See Table 13 and Table 14 for GPI event number assignments for rows and columns. 50 Microsecond Interrupt Configuration The ADP5588 gives the user the flexibility of deasserting the interrupt for 50 μs while there is a pending event. When the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is already asserted results in a 50 μs deassertion. When the INT_CFG bit is cleared, processor interrupt remains asserted if the host tries to clear the interrupt. This feature is particularly useful for software development and edge triggering applications. COMPARATOR 1 INTERRUPT KEY EVENT INTERRUPT KEYLOCK INTERRUPT OVERFLOW INTERRUPT COMPARATOR 2 INTERRUPT GPIO INTERRUPT INT OR INTERRUPT CONFIGURATION OVR_FLOW_ IEN K_LCK_IM GPI_IEN KE_IEN GPIEM_ CFG KEYPAD LOCK INTERRUPT MASK TIMER K_LCK_EN INT LOGIC VCC Figure 9. INT Pin Drive |
类似零件编号 - ADP5588 |
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类似说明 - ADP5588 |
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