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AD9522-1 数据表(PDF) 1 Page - Analog Devices |
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AD9522-1 数据表(HTML) 1 Page - Analog Devices |
1 / 84 page 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.4 GHz VCO AD9522-1 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. FEATURES Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.27 GHz to 2.65 GHz Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVPECL, or LVDS references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 800 MHz LVDS outputs divided into 4 groups Each group of 3 has a 1-to-32 divider with phase delay Additive broadband jitter as low as 242 fs rms Channel-to-channel skew grouped outputs < 60 ps Each LVDS output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz) Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed SPI- and I²C-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures GENERAL DESCRIPTION The AD9522-11 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHz to 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. FUNCTIONAL BLOCK DIAGRAM OPTIONAL REF1 REF2 CLK LF DIVIDER AND MUXES ZERO DELAY CP VCO STATUS MONITOR SPI/I2C CONTROL PORT AND DIGITAL LOGIC EEPROM AD9522 OUT0 OUT1 OUT2 DIV/Φ OUT3 OUT4 OUT5 DIV/Φ OUT6 OUT7 OUT8 DIV/Φ OUT9 OUT10 OUT11 DIV/Φ LVDS/ CMOS REFIN REFIN Figure 1. The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset. The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs. Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set. The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. The AD9522 is specified for operation over the standard industrial range of −40°C to +85°C. The AD9520-1 is an equivalent part to the AD9522-1 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-1 is used, it is referring to that specific member of the AD9522 family. |
类似零件编号 - AD9522-1 |
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类似说明 - AD9522-1 |
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