AD9520-1BCPZ-REEL7 datasheet(11/84 Pages) AD

部件名	AD9520-1BCPZ-REEL7

功能描述	12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO

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制造商	AD [Analog Devices]

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11 / 84 page

AD9520-1

Rev. 0 | Page 11 of 84

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL ABSOLUTE PHASE NOISE

Internal VCO; direct-to-LVPECL output and for

loop bandwidths < 1 kHz

VCO = 2.65 GHz; Output = 2.65 GHz

@ 1 kHz Offset

−49

dBc/Hz

@ 10 kHz Offset

−80

dBc/Hz

@ 100 kHz Offset

−105

dBc/Hz

@ 1 MHz Offset

−125

dBc/Hz

@ 10 MHz Offset

−140

dBc/Hz

@ 40 MHz Offset

−146

dBc/Hz

VCO = 2.475 GHz; Output = 2.475 GHz

@ 1 kHz Offset

−50

dBc/Hz

@ 10 kHz Offset

−82

dBc/Hz

@ 100 kHz Offset

−107

dBc/Hz

@ 1 MHz Offset

−126

dBc/Hz

@ 10 MHz Offset

−141

dBc/Hz

@ 40 MHz Offset

−146

dBc/Hz

VCO = 2.3 GHz; Output = 2.3 GHz

@ 1 kHz Offset

−54

dBc/Hz

@ 10 kHz Offset

−84

dBc/Hz

@ 100 kHz Offset

−109

dBc/Hz

@ 1 MHz Offset

−128

dBc/Hz

@ 10 MHz Offset

−142

dBc/Hz

@ 40 MHz Offset

−146

dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical

setup where the reference source is

clean, so a wider PLL loop bandwidth is

used; reference = 15.36 MHz; R DIV = 1

VCO = 2.458 GHz; LVPECL = 245.76 MHz; PLL LBW = 55 kHz

152

fs rms

Integration BW = 200 kHz to 10 MHz

328

fs rms

Integration BW = 12 kHz to 20 MHz

VCO = 2.458 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz

155

fs rms

Integration BW = 200 kHz to 10 MHz

323

fs rms

Integration BW = 12 kHz to 20 MHz

VCO = 2.458 GHz; LVPECL = 61.44 MHz; PLL LBW = 55 kHz

173

fs rms

Integration BW = 200 kHz to 10 MHz

336

fs rms

Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical

setup where the reference source is

jittery, so a narrower PLL loop bandwidth

is used; reference = 19.44 MHz; R DIV = 162

VCO = 2.488 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz

582

fs rms

Integration BW = 12 kHz to 20 MHz

VCO = 2.458 GHz; LVPECL = 122.88 MHz; PLL LBW = 1.8 kHz

574

fs rms

Integration BW = 12 kHz to 20 MHz

类似零件编号 - AD9520-1BCPZ-REEL7

制造商	部件名	数据表	功能描述
Analog Devices	AD9520-1BCPZ-REEL7	1Mb / 80P	12 LVPECL/24 CMOS Output Clock Generator

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类似说明 - AD9520-1BCPZ-REEL7

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Analog Devices	AD9520-4	1Mb / 84P	12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO REV. 0
	AD9520-3	1Mb / 84P	12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO REV. 0
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	AD9522-1	1Mb / 84P	12 LVDS/24 CMOS Output Clock Generator with Integrated 2.4 GHz VCO REV. 0
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	AD9522-2	1Mb / 84P	12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO REV. 0

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