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AD9230BCPZ11-200 数据表(PDF) 5 Page - Analog Devices |
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AD9230BCPZ11-200 数据表(HTML) 5 Page - Analog Devices |
5 / 28 page AD9230-11 Rev. 0 | Page 5 of 28 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 3. Parameter1 Temp Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full AGND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage (VIH) Full 1.2 3.6 V Low Level Input Voltage (VIL) Full 0 0.8 V High Level Input Current (IIH) Full −10 +10 μA Low Level Input Current (IIL) Full −10 +10 μA Input Resistance (Differential) Full 16 20 24 kΩ Input Capacitance Full 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × AVDD V Logic 0 Voltage Full 0.2 × AVDD V Logic 1 Input Current (SDIO) Full 0 μA Logic 0 Input Current (SDIO) Full −60 μA Logic 1 Input Current (SCLK, PWDN, CSB, RESET) Full 55 μA Logic 0 Input Current (SCLK, PWDN, CSB, RESET) Full 0 μA Input Capacitance 25°C 4 pF LOGIC OUTPUTS2 VOD Differential Output Voltage Full 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 V Output Coding Twos complement, gray code, or offset binary (default) 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 LVDS RTERMINATION = 100 Ω. |
类似零件编号 - AD9230BCPZ11-200 |
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类似说明 - AD9230BCPZ11-200 |
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