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AD8366 数据表(PDF) 6 Page - Analog Devices

部件名 AD8366
功能描述  DC to 500 MHz, Dual Digital Gain Trim Amplifier
Download  13 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8366 数据表(HTML) 6 Page - Analog Devices

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AD8366
Preliminary Technical Data
Rev. PrC | Page 6 of 13
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
BIT0/CS
2
BIT1/SDAT
3
BIT2/SCLK
4
BIT3
5
OCOM
6
BIT4
7
BIT5
8
DENA
24
23
22
21
20
19
18
17
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
TOP VIEW
AD8366
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 8, 13, 28
VPSIA, VPSIB,
VPSOA, VPSOB
Input and Output Stage Positive Supply Voltage. 4.5 V − 5.5 V.
2, 3, 6, 7
IPPA, IPMA,
IPPB, IPMB
Differential Inputs
4
ENBL
Chip Enable. Pull high to enable.
5, 20
ICOM, OCOM
Input and Output Stage Common. Connect via lowest possible impedance to external circuit
common
9, 32
DECA, DECB
Vpos/2 Reference Output Decoupling. Connect decoupling capacitor to circuit common.
10, 31
OFSA, OFSB
Output Offset Correction Loop Compensation. Connect capacitor to circuit common. Tie to
common to disable.
11, 30
CCMA, CCMB
Output Common-mode Centering Loop Compensation. Connect capacitor to circuit common
12, 29
VCMB, VCMA
Output Common-mode Setpoint. Defaults to Vpos/2 if left open
14, 15, 26, 27
OPPB, OPMB,
OPMA, OPPA
Differential Outputs
16, 17
DENB, DENA
Data enable . Pull high to address each or both channels for parallel load. Not used in serial mode.
18, 19, 21, 22, 23, 24
BIT5, BIT4, BIT3,
BIT2, BIT1, BIT0
Parallel data path for SENB pulled low. For SENB pulled high, BIT0 becomes a chip-select (CS), BIT1
becomes serial data input, SDAT, and BIT2 becomes serial clock, SCLK. BIT3-BIT5 are not used in
the serial mode
25
SENB
Serial interface enable. Pull high for serial; pull low for parallel.


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