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AD5627R 数据表(PDF) 7 Page - Analog Devices |
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AD5627R 数据表(HTML) 7 Page - Analog Devices |
7 / 32 page AD5627R/AD5647R/AD5667R, AD5627/AD5667 Rev. 0 | Page 7 of 32 Parameter Conditions2 Min Max Unit Description t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, CB = 400 pF 20 80 ns t13 Standard mode 10 ns LDAC pulse width low Fast mode 10 ns High speed mode 10 ns t14 Standard mode 300 ns Falling edge of 9th SCL clock pulse of last byte of valid write to LDAC falling edge Fast mode 300 ns High speed mode 30 ns t15 Standard mode 20 ns CLR pulse width low Fast mode 20 ns High speed mode 20 ns tSP4 Fast mode 0 50 ns Pulse width of spike suppressed High speed mode 0 10 ns 1 See Figure 3. High speed mode timing specification applies only to the AD5627RBRMZ-2/AD5627BRMZ-2REEL7 and AD5667RBRMZ-2/AD5667BRMZ-2REEL7. 2 CB refers to the capacitance on the bus line. 3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode. SCL SDA PS S P t8 t6 t5 t3 t10 t9 t4 t6 t1 t2 t11 t12 t14 CLR t13 t15 LDAC* t7 *ASYNCHRONOUS LDAC UPDATE MODE. Figure 3. 2-Wire Serial Interface Timing Diagram |
类似零件编号 - AD5627R_07 |
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类似说明 - AD5627R_07 |
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