2
DATEL, Inc., Mansfield, MA 02048 (USA)
• Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 • E–mail: sales@datel.com • Internet: www.datel.com
ADC-30634/ADC-30720
®
®
PERFORMANCE
MIN.
TYP.
MAX.
UNITS
Int. Linearity Over Temp.
(ref. unadjusted)
End-point
—
±2.3
±2.6
LSB
Best-fit Line
—
±1.8
±2.0
LSB
Zero-Scale Offset
—
±2.5
±4
LSB
(Code "0" to "1" transition)
Gain error, @ +25°C
—
±1
±1.75
LSB
Over Temperature
—
±1.5
±2.5
LSB
Differential Gain ➂
—
2
—
%
Differential Phase ➂
—
1.1
—
degrees
Aperture Delay
—
8
—
ns
Aperture Jitter
—
50
—
ps
Harmonic Distortion
(8MHz second order harm.)
–40
–46
—
dB
Ref. bandwidth
(See tech note 5)
—
10
—
MHz
Power Supply Rejection
—
±0.02
±0.05
%FSR/%Vs
No Missing Codes
Over the operating temperature range
POWER REQUIREMENTS
Power Supply Range (+V
DD)
+3.0
+5.0
+5.5
Volts
Power Supply Current
+25°C
—
+120
+160
mA
+125°C
—
+100
+125
mA
–55°C
—
+135
+175
mA
Power Dissipation
+25°C
—
660
880
mW
+125°C
—
550
690
mW
–55°C
—
745
965
mW
PHYSICAL ENVIRONMENTAL
Operating Temp. Range, Case:
MM/LM/QL Versions
–55
—
+125
°C
Storage Temp. Range
–65
—
+150
°C
Package Type
DIP
24-pin ceramic DIP
LCC
24-pin ceramic LCC
PARAMETERS
LIMITS
UNITS
Power Supply Voltage (V
DD Pin 1, 10, 19)
–0.5 to +7
Volts
Digital Inputs
–0.5 to +5.5
Volts
Analog Input
–0.5 to (+V
DD +0.5)
Volts
Reference Inputs
–0.5 to (+V
DD +0.5)
Volts
Digital Outputs
–0.5 to +5.5
Volts
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
+300 max.
°C
Storage Temperature
–65 to +150
°C
FUNCTIONAL SPECIFICATIONS
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
ABSOLUTE MAXIMUM RATINGS
ANALOG INPUT
MIN.
TYP.
MAX.
UNITS
Single-Ended, Non-Isolated
Input Range DC - 20MHz
0
–
+5.0
Volts
Analog Input Capacitance
(static - Pin 5 to 7)
–
20
–
pF
(dynamic - Pin 5 to 7)
–
64
–
pF
Reference Ladder Resistance
–
500
–
Ohms
Reference Input (Note 5)
–0.5
–
VDD +0.5
Volts
DIGITAL INPUTS
Logic Levels
Logic "1"
3.2
—
—
Volts
Logic "0"
—
—
0.8
Volts
Logic Loading
Logic Loading "1"
—
+1
+5
mA
Logic Loading "0"
—
+1
+5
mA
Clock Low Pulse Width
15
25
—
nSec
DIGITAL OUTPUTS
Logic Levels
Logic "1"
2.4
4.5
5.0
Volts
Logic "0"
—
—
0.4
Volts
Logic Loading
Logic Loading "1"
4
—
—
mA
Logic Loading "0"
4
—
—
mA
Output Data Valid Delay From
Rising Clock Edge
99% probability
5
10
15
nSec
100% probability
+25°C
5
10
25
nSec
–55°C to +125°C
—
—
40
nSec
Data Output Resolution
8
—
—
Bits
Data Coding
Straight binary
PERFORMANCE
Sampling Rate ➁
15
20
—
MSPS
Full Power Bandwidth
10
—
—
MHz
Diff. Linearity @ +25°C
(See tech note 7)
Code Transitions
—
±0.5
±1.0
LSB
Center of Codes
—
±0.25
—
LSB
Diff. Linearity Over Temp.
Code Transitions
—
±0.5
±1.0
LSB
Center of Codes
—
±0.25
—
LSB
Int. Linearity @ +25°C
(See tech note 4)(ref. adjusted)
End-point
—
—
±1/2
LSB
Best-fit Line
—
—
±1/2
LSB
Int. Linearity Over Temp.
(ref. adjusted)
Best-fit Line
—
±1/2
±1
LSB
Int. Linearity @ +25°C
(ref. unadjusted)
End-point
—
±2
±2.5
LSB
Best-fit Line
—
±1.6
±1.9
LSB
Footnotes:
➀ Maximum input impedance is a function of clock frequency.
➁ At full-power input.
➂ For 10-step, 40 IRE NTSC ramp test.
TECHNICAL NOTES
1. The Reference ladder is floating with respect to VDD
and may be referenced anywhere within the specified
limits. AC modulation of the reference voltage may also
be utilized; contact DATEL for further information.
2. Clock Pulse Width – To improve performance when input
signals may exceed Nyquist bandwidths, the clock duty
cycle can be adjusted so that the low portion (sample
mode) of the clock pulse is 15nSec wide. Reducing
the sampling time period minimizes the amount the
input voltage slews and prevents the comparators from
saturating.
3. A full-scale input produces all "1" on the data outputs.
4. DATEL uses the conservative definitions when specifying
Intergal Linearity (end-point) and Differential Linearity (code
transition). The specifications using the less conservative
definition have also been provided as a comparative
specification for products specified this way.