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LC01700PW 数据表(PDF) 8 Page - Sanyo Semicon Device |
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LC01700PW 数据表(HTML) 8 Page - Sanyo Semicon Device |
8 / 18 page LC01700PW No.A1337-8/18 5. Software reset After power ON, enter the signal as follows to avoid malfunction. If the communication is interrupted (microcomputer reset, etc.), entry of the following signal enables normal operation. 6. Electrical Specification and Timing for I/O Stages Bus line characteristics FAST-MODE Parameter Symbol min max unit For SCL = 100kHz (Example) SCL clock frequency fSCL - 400 kHz 100 SDA, SCL fall time t1 20+0.1Cb 300 ns - SDA, SCL rise time t2 20+0.1Cb 300 ns - SCL "H" time t3 0.6 - µs 3 SCL "L" time t4 1.3 - µs 7 "Start" condition hold time t5 0.6 - µs 10 Data hold time For I 2C bus device t6 0.3 - µs - Data setup time t7 0.1 - µs 3 "Stop" condition setup time t8 0.6 - µs 10 "Stop"-"Start" bus free time t9 1.3 - µs 20 "Start" condition setup time t10 0.6 - µs - Bus line capacitive load Cb - 400 pF - SDA SCL P Sr S 1 2 789 START condition STOP condition reperted START condition SDA t1 t10 SCL START condition STOP condition t2 t2 t4 t1 t7 t9 t8 t3 t6 t5 |
类似零件编号 - LC01700PW |
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类似说明 - LC01700PW |
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