MCZ33996EKR2 datasheet(7/24 Pages) FREESCALE

部件名	MCZ33996EKR2

功能描述	16 Output Switch with SPI Control

Download	24 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

标志

7 / 24 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

33996

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions of 3.1 V

≤ SOPWR ≤ 5.5 V, 5.0 V ≤ VPWR ≤ 18 V, -40°C ≤ TA ≤ 125°C unless otherwise

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING (VPWR)

Output Slew Rate

RL = 60Ω (15)

SR

1.0

2.0

10

V/

μs

Output Turn ON Delay Time (16)

tDLY(ON)

1.0

2.0

10

μs

Output Turn OFF Delay Time (16)

tDLY(OFF)

1.0

4.0

10

μs

Output ON Short Fault Disable Report Delay (17)

tDLY(SHORT)

100

–

450

μs

Output OFF Open Fault Delay Time (17)

tDLY(OPEN)

100

–

450

μs

Output PWM Frequency

tFREQ

–

2.0

kHz

DIGITAL INTERFACE TIMING (CS, SO, SI, SCLK) (23)

Required Low State Duration on VPWR for Reset

VPWR ≤ 0.2V (18)

tRST

–

10

μs

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

tLEAD

100

–

ns

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

tLAG

50

–

ns

SI to Falling Edge of SCLK

Required Setup Time

tSI(su)

16

–

ns

Falling Edge of SCLK to SI

Required Hold Time

tSI(hold)

20

–

ns

SI, CS, SCLK Signal Rise Time (19)

tR(SI)

–

5.0

–

ns

SI, CS, SCLK Signal Fall Time (19)

tF(SI)

–

5.0

–

ns

Time from Falling Edge of CS to SO Low-impedance (20)

tSO(EN)

–

50

ns

Time from Rising Edge of CS to SO High-impedance (21)

tSO(DIS)

–

50

ns

Time from Rising Edge of SCLK to SO Data Valid (22)

tVALID

–

25

80

ns

Notes

15.

Output slew rate measured across a 60

Ω resistive load.

16.

Output turn ON and OFF delay time measured from 50% rising edge of CS to 80% and 20% of initial voltage.

17.

Duration of fault before fault bit is set. Duration between access times must be greater than 450

μs to read faults.

18.

This parameter is guaranteed by design; however, it is not production tested.

19.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

20.

Time required for valid output status data to be available on SO pin.

21.

Time required for output states data to be terminated at SO pin.

22.

Time required to obtain valid data out from SO following the rise of SCLK with 200pF load.

23.

This parameter is guaranteed by design. Production test equipment used 4.16MHz, 5.5/3.1V SPI Interface.

类似零件编号 - MCZ33996EKR2

制造商	部件名	数据表	功能描述
Freescale Semiconductor...	MCZ33996EKR2	610Kb / 23P	16-Output Switch with SPI Control

More results

类似说明 - MCZ33996EKR2

制造商	部件名	数据表	功能描述
Motorola, Inc	MC33996	635Kb / 16P	16-Output Switch with SPI Control
Freescale Semiconductor...	33996	610Kb / 23P	16-Output Switch with SPI Control
Motorola, Inc	MC33999	627Kb / 16P	16-Output Switch with SPI and PWM Control
Freescale Semiconductor...	MC33999	578Kb / 21P	16-Output Switch with SPI and PWM Control
	MCZ33999EK	708Kb / 21P	16-Output Switch with SPI and PWM Control
	33882	688Kb / 27P	Six-Output Low-Side Switch with SPI and Parallel Input Control
Motorola, Inc	MC33882	779Kb / 24P	Six-Output Low-Side Switch with SPI and Parallel Input Control
Freescale Semiconductor...	33882	1Mb / 31P	Six Output Low Side Switch with SPI and Parallel Input Control
NXP Semiconductors	MC33882	1Mb / 30P	Six Output Low-side Switch with SPI and Parallel Input Control Rev. 11.0, 11/2014
Infineon Technologies A...	TLE8110ED	2Mb / 74P	Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Rev. 1.0 2018-03-07