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MC13212 数据表(PDF) 15 Page - Freescale Semiconductor, Inc |
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MC13212 数据表(HTML) 15 Page - Freescale Semiconductor, Inc |
15 / 70 page MC13211/212/213 Technical Data, Rev. 1.4 Freescale Semiconductor 15 3.2 SPI Features • MCU bus master • Modem bus slave • Programmable SPI clock rate; maximum rate is 8 MHz • Double-buffered transmit and receive at MCU • Serial clock phase and polarity must meet modem requirements (MCU control bits • Slave select programmed to meet modem protocol 3.3 SPI System Block Diagram Figure 5 shows the SPI system level diagram. Figure 5. SPI System Block Diagram Figure 5 shows the SPI modules of the MCU and modem in the master-slave arrangement. The MCU (master) initiates all SPI transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. Although the SPI interface supports simultaneous data exchange between master and slave, the modem SPI protocol only uses data exchange in one direction at a time. The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS1 pin). 7 6 5 4 3 2 1 0 SPI SHIFTER CLOCK GENERATOR 7 6 5 4 3 2 1 0 SPI SHIFTER PTE2/SS1 SPSCK1 MISO1 MOS1 CE SPICLK MISO MOSI MCU (MASTER) MODEM (SLAVE) |
类似零件编号 - MC13212 |
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类似说明 - MC13212 |
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