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MC33790DWR2 数据表(PDF) 8 Page - Freescale Semiconductor, Inc

部件名 MC33790DWR2
功能描述  Two-Channel Distributed System Interface (DSI) Physical Interface Device
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MC33790DWR2 数据表(HTML) 8 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
8
Freescale Semiconductor
33790
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33790 is designed to provide the interface between
logic and the DSI bus. It accepts signals with a typical 0 V to
5.0 V logic level to control the state of the bus output (Idle
Level, Logic High Level, Logic Low Level, and High
Impedance). It detects the current drawn from the bus output
during signaling and outputs a 0 V to 5.0 V logic level
corresponding to the bus current being above (Logic [1] out)
the bus return logic [1] current or below (Logic [0] out). The
33790 contains current limiting of the bus outputs as required
by the DSI Bus specification and thermal shutdown to protect
itself from damage. Two independent DSI bus outputs are
provided by the IC.
FUNCTIONAL TERMINAL DESCRIPTION
Bus Driver and Receiver
The Wave-Shaper converts the 0 V to 5.0 V logic inputs
from DSIxF (frame) and DSIxS (signal) to a wave-shaped
signal on the DSIxO output, as shown in the timing diagrams
in Figure 2, page 2, and the truth table in Table 5. The Bus
Current Sense detects the current being drawn by the
device(s) on the bus during signalling (DSIxF=0). If the
current is above a set level, DSIxR will be high; otherwise, it
is low. Due to the variations in the turnaround time (tTAT) from
slave devices and bus delays, DSIxR should be sampled on
the falling edge of DSIxS and on the rising edge of DSIxF (for
the last return bit).
The current for the idle state is from the supply connected
to VSUP and this supply should not be current limited below
250 mA per channel. During idle state, the voltage on the DSI
bus will be very close to the VSUP voltage.
Internal thermal shutdown circuitry and current limit
individually protect the DSIxO outputs from shorts to battery
and ground.
Typically, the thermal shutdown occurs between 160°C
and 170°C. If the junction temperature rises above this
temperature, the internal TxLIM bit is asserted, and the output
drivers for DSIxO are disabled by the thermal shutdown
circuitry. The output drivers remain off until the junction
temperature decreases below approximately 155°C, at which
time the thermal shutdown circuitry turns off and the outputs
are re-enabled. Each DSIxO output has a unique thermal
sense and shutdown circuit, so a short on one channel does
not affect the other channel.
Charge Pump
The charge pump uses on-board capacitors to step the
input voltage up to the voltage needed to drive the on-board
transmitter FETs. A filter/storage capacitor is connected to
CPCAP to hold the stepped-up voltage.
Input Pullups and Pulldowns
Internal current pullups are used on the DSIxF pins and
pulldowns on the DSIxS pins. If these pins are left
unconnected, their associated DSI bus will go to the unused
(high impedance) state.
Table 5. DSI Bus Truth Table
DSIxF
DSIxS
TxLIM
DSIxR
DSIxO
0
0
0
Not Defined
Low (1.5 V)
0
1
0
Not Defined
High (4.5 V)
0
0
Return Data
Unchanged
X
0
Return Data
Unchanged
1
0
0
0
High Impedance
11
0
0
Idle
≥VSUP-0.5 V
X
X
1
1
High Impedance


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