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ST6200C 数据表(PDF) 6 Page - STMicroelectronics

部件名 ST6200C
功能描述  8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
Download  100 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST6200C 数据表(HTML) 6 Page - STMicroelectronics

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ST6200C/ST6201C/ST6203C
6/100
1 INTRODUCTION
The ST6200C, 01C and 03C devices are low cost
members of the ST62xx 8-bit HCMOS family of mi-
crocontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are
based on a building block approach: a common
core is surrounded by a number of on-chip periph-
erals.
The ST62E01C is the erasable EPROM version of
the ST62T00C, T01 and T03C devices, which may
be used during the development phase for the
ST62T00C, T01 and T03C target devices, as well
as the respective ST6200C, 01C and 03C ROM
devices.
OTP and EPROM devices are functionally identi-
cal. OTP devices offer all the advantages of user
programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
The ROM based versions offer the same function-
ality, selecting the options defined in the program-
mable option bytes of the OTP/EPROM versions
in the ROM option list (See Section 12.6 on page
92).
The ST62P00C, P01C and P03C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T00C, T01 and T03C OTP devic-
es.
They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer (See Section 12 on page 86).
These compact low-cost devices feature a Timer
comprising an 8-bit counter with a 7-bit program-
mable prescaler, an 8-bit A/D Converter with 4 an-
alog inputs (depending on device, see device
summary on page 1) and a Digital Watchdog tim-
er, making them well suited for a wide range of au-
tomotive, appliance and industrial applications.
For easy reference, all parametric data are located
in Section 11 on page 58.
Figure 1. Block Diagram
NMI
INTERRUPTS
PROGRAM
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
OSCILLATOR
RESET
DATA ROM
USER
SELECTABLE
DATA RAM
64 Bytes
PORT A
PORT B
TIMER
8-BIT CORE
8-BIT *
A/D CONVERTER
PA1..PA3 (20mA Sink)
PB0..PB1
VDD VSS OSCin OSCout
RESET
WATCHDOG
:
MEMORY
TIMER
(1K or 2K Bytes)
PB3, PB5..PB7 / Ain*
* Depending on device. Please refer to I/O Port section.
VPP
4


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