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STPCE1HEBC 数据表(PDF) 5 Page - STMicroelectronics |
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STPCE1HEBC 数据表(HTML) 5 Page - STMicroelectronics |
5 / 87 page GENERAL DESCRIPTION Release 1.3 - January 29, 2002 5/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1. GENERAL DESCRIPTION At the heart of the STPC Elite is an advanced processor block that includes a powerful x86 processor core along with a 64-bit SDRAM controller, a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus) and EIDE controller. The processor bus runs at the speed of the processor (x1 mode) or half the speed (x2 mode). The STMicroelectronics x86 processor core is embedded with standard and application specific peripheral modules on the same silicon die. The core has all the functionality of the ST standard x86 processor products, including the low power System Management Mode (SMM). System Management Mode (SMM) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. While running in isolated SMM address space, the SMM interrupt routine can execute without interfering with the operating system or application programs. The ‘standard’ PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated with the x86 processor core. The PCI bus is the main data communication link to the STPC Elite chip. The STPC Elite translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports generation of Configuration cycles on the PCI bus. The STPC Elite, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devices. The STPC Elite integrates an ISA bus controller. Peripheral modules such as parallel and serial communications ports, keyboard controllers and additional ISA devices can be accessed by the STPC Elite chip set through this bus. An industry standard EIDE (ATA 2) controller is built in to the STPC Elite and connected internally via the PCI bus. 1.1. MEMORY CONTROLLER The STPC handles the memory data (DATA) bus directly, controlling from 8 to 128 MBytes. The SDRAM controller supports accesses to the Memory Banks to/from the CPU (via the host). Parity is not supported. The SDRAM controller only supports 64 bit wide Memory Banks. Four Memory Banks (if DIMMS are used; Single sided or two double-sided DIMMs) are supported in the following configurations (see Table 1-1) The SDRAM Controller supports buffered or unbuffered SDRAM but not EDO or FPM modes. SDRAMs must support Full Page Mode Type access. The STPC Memory Controller provides various programmable SDRAM parameters to allow the SDRAM interface to be optimized for different processor bus speeds SDRAM speed grades and CAS Latency. 1.2. POWER MANAGEMENT The STPC Elite core is compliant with the Advanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal computers. The Power Management Unit (PMU) module controls the power consumption, providing a comprehensive set of features that controls the power usage and supports compliance with the United States Environmental Protection Agency's Energy Star Computer Program. The PMU provides the following hardware structures to assist the software in managing the system power consumption: - System Activity Detection. Table 1-1. Memory configurations Memory Bank size Number Organisa tion Device Size 1Mx64 4 1Mx16 16Mbits 2Mx64 8 2Mx8 4Mx64 16 4Mx4 4Mx64 4 2Mx16x2 64Mbits 8Mx64 8 4Mx8x2 16Mx64 16 8Mx4x2 4Mx64 4 1Mx16x4 8Mx64 8 2Mx8x4 32Mx64 16 4Mx4x4 16Mx64 8 2Mx16x2 128Mbits 32Mx64 16 4Mx8x4 |
类似零件编号 - STPCE1HEBC |
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类似说明 - STPCE1HEBC |
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