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LFE26E-5F900I 数据表(PDF) 34 Page - Lattice Semiconductor |
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LFE26E-5F900I 数据表(HTML) 34 Page - Lattice Semiconductor |
34 / 386 page 2-31 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Table 2-12. PIO Signals List PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selec- tion logic. Input Register Block The input register blocks for PIOs in left, right and bottom edges contain delay elements and registers that can be used to condition high-speed interface signals, such as DDR memory interfaces and source synchronous inter- faces, before they are passed to the device core. Figure 2-29 shows the diagram of the input register block for left, right and bottom edges. The input register block for the top edge contains one memory element to register the input signal as shown in Figure 2-30. The following description applies to the input register block for PIOs in the left, right and bottom edges of the device. Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and, in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows three modes of operation. In the single data rate (SDR) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. In DDR Mode, two registers are used to sample the data on the positive and negative edges of the DQS signal, creating two data streams, D0 and D1. These two data streams are synchronized with the system clock before entering the core. Further discussion on this topic is in the DDR Memory section of this data sheet. Name Type Description CE0, CE1 Control from the core Clock enables for input and output block flip-flops CLK0, CLK1 Control from the core System clocks for input and output blocks ECLK1, ECLK2 Control from the core Fast edge clocks LSR Control from the core Local Set/Reset GSRN Control from routing Global Set/Reset (active low) INCK 2 Input to the core Input to Primary Clock Network or PLL reference inputs DQS Input to PIO DQS signal from logic (routing) to PIO INDD Input to the core Unregistered data input to core INFF Input to the core Registered input on positive edge of the clock (CLK0) IPOS0, IPOS1 Input to the core Double data rate registered inputs to the core QPOS0 1, QPOS11 Input to the core Gearbox pipelined inputs to the core QNEG0 1, QNEG11 Input to the core Gearbox pipelined inputs to the core OPOS0, ONEG0, OPOS2, ONEG2 Output data from the core Output signals from the core for SDR and DDR operation OPOS1 ONEG1 Tristate control from the core Signals to Tristate Register block for DDR operation DEL[3:0] Control from the core Dynamic input delay control bits TD Tristate control from the core Tristate signal from the core used in SDR operation DDRCLKPOL Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block DQSXFER Control from core Controls signal to the Output block 1. Signals available on left/right/bottom only. 2. Selected I/O. |
类似零件编号 - LFE26E-5F900I |
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类似说明 - LFE26E-5F900I |
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