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LFXP6E-4QN208I 数据表(PDF) 6 Page - Lattice Semiconductor |
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LFXP6E-4QN208I 数据表(HTML) 6 Page - Lattice Semiconductor |
6 / 130 page 2-3 Architecture Lattice Semiconductor LatticeXP Family Data Sheet Slice Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks. There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU). There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice. Figure 2-3. Slice Diagram LUT4 & CARRY LUT4 & CARRY Slice A0 B0 C0 D0 FF/ Latch OFX0 F0 Q0 A1 B1 C1 D1 CI CI CO CO F SUM CE CLK LSR FF/ Latch OFX1 F1 Q1 F SUM D D M1 To / From Different slice / PFU Fast Carry Out (FCO) To / From Different slice / PFU Fast Carry In (FCI) LUT Expansion Mux M0 OFX0 From Routing To Routing Control Signals selected and inverted per slice in routing Note: Some interslice signals are not shown. |
类似零件编号 - LFXP6E-4QN208I |
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类似说明 - LFXP6E-4QN208I |
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