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LFXP6E-3QN208C 数据表(PDF) 10 Page - Lattice Semiconductor |
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LFXP6E-3QN208C 数据表(HTML) 10 Page - Lattice Semiconductor |
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10 / 130 page  2-7 Architecture Lattice Semiconductor LatticeXP Family Data Sheet Figure 2-5. Primary Clock Sources Secondary Clock Sources LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6. From Routing Clock Input From Routing PLL Input Clock Input PLL Input PLL Input Clock Input PLL Input From Routing Clock Input From Routing PLL PLL PLL PLL 20 Primary Clock Sources To Quadrant Clock Selection Note: Smaller devices have two PLLs. |
类似零件编号 - LFXP6E-3QN208C |
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类似说明 - LFXP6E-3QN208C |
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