数据搜索系统,热门电子元器件搜索 |
|
LC5512MB-5FN208I 数据表(PDF) 11 Page - Lattice Semiconductor |
|
LC5512MB-5FN208I 数据表(HTML) 11 Page - Lattice Semiconductor |
11 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 11 Pseudo Dual-Port SRAM Mode In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM. Write data, write address, chip select and write enable signals are always synchronous (registered). The read data and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for the various registers. Figure 10. Pseudo Dual-Port SRAM Block Diagram Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode Register Input Source Write Address, Write Data, Write Enable, and Write Chip Select Clock WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be inverted if desired. Clock Enable WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can be inverted if desired. Reset Created by the logical OR of the global reset signal and RST. RST may have inversion if desired. Read Data and Read Address Clock RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be inverted if desired. Clock Enable RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can be inverted if desired. Reset Created by the logical OR of the global reset signal and RST. RST may have inversion if desired. ‘ ‘ 68 Inputs From Routing 16,384 bit Pseudo Dual Port SRAM Array Write Address (WAD[0:8-13]) Write Clk Enable (WCEN) Write Clock (WCLK) Read Address (RAD[0:8-13]) Write Enable (WE) Write Chip Sel (WCS[0,1]) Reset (RST) Read Clk Enable (RCEN) Read Clock (RCLK) Write Data (WD[0:0,1,3,7,15,31]) RESET CLK0 CLK3 CLK1 CLK2 Read Data (RD[0:0-15]) |
类似零件编号 - LC5512MB-5FN208I |
|
类似说明 - LC5512MB-5FN208I |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |