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ST7F10BF0B3TR 数据表(PDF) 8 Page - STMicroelectronics |
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ST7F10BF0B3TR 数据表(HTML) 8 Page - STMicroelectronics |
8 / 159 page ST7LITE1xB 8/159 Notes: 1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground. 2. When the pin is configured as analog input, positive and negative current injections are not allowed. 3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 32 on page 50). 12 10 10 PA6 /MCO/ ICCCLK/BREAK I/O CT X ei1 XX Port A6 Main Clock Output or In Circuit Communication Clock or External BREAK Caution: During normal operation this pin must be pulled- up, inter- nally or externally (external pull-up of 10k mandatory in noisy environ- ment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up 13 11 11 PA5 /ICCDATA/ ATPWM3 I/O CT HS X ei1 XX Port A5 In Circuit Communication Data or Auto-Reload Timer PWM3 14 12 12 PA4/ATPWM2 I/O CT HS X XX Port A4 Auto-Reload Timer PWM2 15 13 - PA3/ATPWM1 I/O CT HS X ei0 XX Port A3 Auto-Reload Timer PWM1 16 14 13 PA2/ATPWM0 I/O CT HS X XX Port A2 Auto-Reload Timer PWM0 17 15 - PA1/ATIC I/O CT HS X XX Port A1 Auto-Reload Timer Input Capture 18 16 14 PA0/LTIC I/O CT HS X XX Port A0 Lite Timer Input Capture 19 17 15 OSC2/PC1 I/O X X Port C13) Resonator oscillator inverter out- put 20 18 16 OSC1/CLKIN/PC0 I/O X X Port C03) Resonator oscillator inverter input or External clock input Pin No. Pin Name Level Port / Control Main Function (after reset) Alternate Function Input Output 1 |
类似零件编号 - ST7F10BF0B3TR |
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类似说明 - ST7F10BF0B3TR |
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