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STA680Q 数据表(PDF) 10 Page - STMicroelectronics |
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STA680Q 数据表(HTML) 10 Page - STMicroelectronics |
10 / 43 page System overview STA680 10/43 2.3.3 Other The spare computation power and memories are suitable to implement other specific algorithms or custom software application. For example sophisticated sound and audio processing could be implemented on the HD Radio decompressed audio. Audio output can be provided either in IIS master clock mode or in slave mode with the on-chip audio sample rate converter. Up to six audio channels may be provided in a standard configuration. Another possibility is to implement on the STA680 the handling of data services. 2.4 Overview of main functional blocks 2.4.1 Adjacent channel filter This module performs time domain filtering specifically for IBOC system. It receives a complex base-band IBOC signal input from SRC module and pre-conditions the signal for subsequent modem processing. The module is a front end device. 2.4.2 HiFi2 The HiFi2 is a signal processing engine specifically designed to provide high quality 24-bit audio processing. The HiFi2 is also useful for advanced data applications such as storage and playback of received audio and conditional access processing. The HiFi2 leverages the Tensilica Xtensa LX engine with additional useful hardware capabilities such as: ● Specialized instructions for 24-bit Audio MAC & stream coding ● Dual MAC (each supports 24x24 and 32x16 bit format) ● Huffman Encode / Decode and truncate functions ● Two way SIMD arithmetic and Boolean operations 2.4.3 Vectra The Vectra LX is a powerful, configurable 32-bit RISC engine optimized for DSP with VLIW capabilities. The Vectra LX on board the STA680 includes eight MAC units, sixteen 160-bit vector operation registers, and a number of SIMD arithmetic instructions. Custom instructions in the Vectra are targeted for DSP applications such as filters and FFTs. The Vectra processor has been further configured with specific instructions for efficient performance on the HD Radio application. 2.4.4 DMA A ten-channel DMA controller is attached to the AHB bus to allow the Vectra and HiFi2 processor cores to move large blocks of data efficiently. Certain channels are dedicated for use with certain hardware blocks because of hardware handshaking signals. 2.4.5 Hardware accelerator (VITERBI) A complex convolutional Viterbi module is designed to fully comply with the HD Radio system. The module supports both K constant of 7 and 9, for IBOC digital FM and AM bands respectively. |
类似零件编号 - STA680Q |
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类似说明 - STA680Q |
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