数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ISPXPLD5000MX 数据表(PDF) 43 Page - Lattice Semiconductor

部件名 ISPXPLD5000MX
功能描述  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
Download  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  LATTICE [Lattice Semiconductor]
网页  http://www.latticesemi.com
标志 LATTICE - Lattice Semiconductor

ISPXPLD5000MX 数据表(HTML) 43 Page - Lattice Semiconductor

Back Button ISPXPLD5000MX Datasheet HTML 39Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 40Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 41Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 42Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 43Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 44Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 45Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 46Page - Lattice Semiconductor ISPXPLD5000MX Datasheet HTML 47Page - Lattice Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 43 / 92 page
background image
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
43
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Units
tPWH
Input clock, high time
80% to 80%
1.2
ns
tPWL
Input clock, low time
20% to 20%
1.2
ns
tR, tF
Input Clock, rise and fall time
20% to 80%
3.0
ns
tINSTB
Input clock stability, cycle to cycle (peak)
+/- 250
ps
fMDIVIN
M Divider input, frequency range
10
320
MHz
fMDIVOUT
M Divider output, frequency range
10
320
MHz
fNDIVIN
N Divider input, frequency range
10
320
MHz
fNDIVOUT
N Divider output, frequency range
10
320
MHz
fVDIVIN
V Divider input, frequency range
100
400
MHz
fVDIVOUT
V Divider output, frequency range
10
320
MHz
tOUTDUTY
Output clock, duty cycle
40
60
%
tJIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean reference.
10 MHz < fMDIVOUT < 20 MHz or
100MHz < fVDIVIN < 160 MHz
1
+/- 250
ps
Clean reference.
20 MHz < fMDIVOUT < 320 MHz and
160MHz < fVDIVIN < 320 MHz
1
+/- 150
ps
TJIT(PERIOD)
2
Output clock, period jitter (peak)
Clean reference.
10 MHz < fMDIVOUT < 20 MHz or
100MHz < fVDIVIN < 160 MHz
1
+/- 300
ps
Clean reference.
20 MHz < fMDIVOUT < 320 MHz and
160MHz < fVDIVIN < 320 MHz
1
+/- 150
ps
tCLK_OUT_DLY
Input clock to CLK_OUT delay
Internal feedback
3.0
ns
tPHASE
Input clock to external feedback delta
External feedback
600
ps
tLOCK
Time to acquire phase lock after input stable
25
us
tPLL_DELAY
Delay increment (Lead/Lag)
Typical = +/- 250ps
+/- 120 +/- 550
ps
tRANGE
Total output delay range (lead/lag)
+/- 0.84 +/- 3.85
ns
tPLL_RSTW
Minimum reset pulse width
1.8
ns
tCLK_IN
3
Global clock input delay
1.0
ns
tPLL_SEC_DELA
Y
Secondary PLL output delay (tPLL_DELAY)
1.5
ns
1. This condition assures that the output phase jitter will remain within specification.
2. Accumulated jitter measured over 10,000 waveform samples.
3. Internal timing for reference only.


类似零件编号 - ISPXPLD5000MX

制造商部件名数据表功能描述
logo
Lattice Semiconductor
ISPXPGA LATTICE-ISPXPGA Datasheet
535Kb / 115P
   ispXPGA Family
ISPXPGA1200 LATTICE-ISPXPGA1200 Datasheet
535Kb / 115P
   ispXPGA Family
ISPXPGA1200E LATTICE-ISPXPGA1200E Datasheet
535Kb / 115P
   ispXPGA Family
ISPXPGA125 LATTICE-ISPXPGA125 Datasheet
535Kb / 115P
   ispXPGA Family
ISPXPGA125E LATTICE-ISPXPGA125E Datasheet
535Kb / 115P
   ispXPGA Family
More results

类似说明 - ISPXPLD5000MX

制造商部件名数据表功能描述
logo
Lattice Semiconductor
LC5256MC LATTICE-LC5256MC Datasheet
427Kb / 92P
   3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD??Family
LC4512Z LATTICE-LC4512Z Datasheet
851Kb / 91P
   3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4032C LATTICE-LC4032C Datasheet
483Kb / 74P
   3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
ISPMACH4000V LATTICE-ISPMACH4000V Datasheet
451Kb / 99P
   3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
logo
Altera Corporation
EPM7064LI44-15 ALTERA-EPM7064LI44-15 Datasheet
1Mb / 66P
   Programmable Logic Device Family
EPM3512AQC208-10N ALTERA-EPM3512AQC208-10N Datasheet
715Kb / 46P
   Programmable Logic Device Family
EPM7064STI44-7N ALTERA-EPM7064STI44-7N Datasheet
1Mb / 66P
   Programmable Logic Device Family
EPF8452AQC160-3 ALTERA-EPF8452AQC160-3 Datasheet
957Kb / 62P
   Programmable Logic Device Family
EPM7064STI44-7 ALTERA-EPM7064STI44-7 Datasheet
1Mb / 66P
   Programmable Logic Device Family
EPM7032LC44-15 ALTERA-EPM7032LC44-15 Datasheet
1Mb / 66P
   Programmable Logic Device Family
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com