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ISPXPLD5000MX Datasheet(数据表) 4 Page - Lattice Semiconductor

部件型号  ISPXPLD5000MX
说明  3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family
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制造商  LATTICE [Lattice Semiconductor]
网页  http://www.latticesemi.com
标志 LATTICE - Lattice Semiconductor

ISPXPLD5000MX Datasheet(HTML) 4 Page - Lattice Semiconductor

  ISPXPLD5000MX 数据表 HTML 1Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 2Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 3Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 4Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 5Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 6Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 7Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 8Page - Lattice Semiconductor ISPXPLD5000MX 数据表 HTML 9Page - Lattice Semiconductor Next Button
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
4
Cascading For Wide Operation
In several modes it is possible to cascade adjacent MFBs to support wider operation. Table 2 details the different
cascading options. There are chains of MFBs in each device which determine those MFBs that are adjacent for the
purposes of cascading. Table 3 indicates these chains. The ispXPLD 5000MX design tools automatically cascade
blocks if required by a particular design.
Table 2. Cascading Modes For Wide Support
Table 3. MFB Cascade Chain
SuperWIDE Logic Mode
In logic mode, each MFB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic
product terms and four control product terms. The MFB has 68 inputs from the Global Routing Pool, which are
available in both true and complement form for every product term. It is also possible to cascade adjacent MFBs to
create a block with 136 inputs. The four control product terms are used for shared reset, clock, clock enable, and
output enable functions. Figure 3 shows the overall structure of the MFB in logic mode while Figure 4 provides a
more detailed view from the perspective of a macrocell slice.
Mode
Cascading Function
Logic
Input Width. Allows two MFBs to act as a 136-input block.
Arithmetic. Allow the carry chain to pass between two MFBs.
FIFO
Memory Width Expansion. Allows MFBs to be cascaded for greater width support.
CAM
Memory Width Expansion. Allows up to four MFBs to be cascaded for greater width support.
Device
MFBs in Cascade Chain
ispXPLD 5256MX
A → B → C → D
H -> G -> F -> E
ispXPLD 5512MX
A → B → C → D → E → F → G → H
P → Ο → N → M → L → K → J → I
ispXPLD 5768MX
D → C → B → A → X → W → V → U → T → S → R → Q
E → F → G → H → I → J → K → L → M → N → O → P
ispXPLD 51024MX
H → G → F → E → D → C → B → A → AF → AE → AD → AC → AB → AA → Z → Y
I → J → K → L → M → N → O → P → Q → R → S → T → U → V → W → X




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