 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
LFE26E-6F256C 数据表(PDF) 18 Page - Lattice Semiconductor |
|
||||||||||||||||||||||||||||||
LFE26E-6F256C 数据表(HTML) 18 Page - Lattice Semiconductor |
|
|
18 / 386 page  2-15 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Primary Clock Routing The clock routing structure in LatticeECP2/M devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-13 shows the clock routing for one quadrant. Each quadrant mux is identical. If desired, any clock can be routed globally Figure 2-13. Per Quadrant Primary Clock Selection Dynamic Clock Select (DCS) The DCS is a smart multiplexer function available in the primary clock routing. It switches between two independent input clock sources without any glitches or runt pulses. This is achieved regardless of when the select signal is tog- gled. There are two DCS blocks per quadrant; in total, there are eight DCS blocks per device. The inputs to the DCS block come from the center muxes. The output of the DCS is connected to primary clocks CLK6 and CLK7 (see Figure 2-13). Figure 2-14 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, please see the list of additional technical documentation at the end of this data sheet. Figure 2-14. DCS Waveforms Secondary Clock/Control Routing Secondary clocks in the LatticeECP2 devices are region-based resources. The benefit of region-based resources is the relatively low injection delay and skew within the region, as compared to primary clocks. EBR/DSP rows and a special vertical routing channel bound the secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP block in the DSP row or the center of the DSP row. Figure 2-15 shows CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 35:1 35:1 35:1 35:1 32:1 32:1 32:1 32:1 35:1 35:1 8 Primary Clocks (CLK0 to CLK7) per Quadrant DCS DCS Primary Clock Sources: PLLs + DLLs + CLKDIVs + PIOs + Routing CLK0 SEL DCSOUT CLK1 |
类似零件编号 - LFE26E-6F256C |
|
类似说明 - LFE26E-6F256C |
|
|
链接网址 |
| 隐私政策 |
| ALLDATASHEETCN.COM |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
