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LFE250SE-6F256C 数据表(PDF) 2 Page - Lattice Semiconductor

部件名 LFE250SE-6F256C
功能描述  LatticeECP2/M Family Data Sheet
Download  386 Pages
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制造商  LATTICE [Lattice Semiconductor]
网页  http://www.latticesemi.com
标志 LATTICE - Lattice Semiconductor

LFE250SE-6F256C 数据表(HTML) 2 Page - Lattice Semiconductor

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1-1
DS1006 Introduction_01.7
June 2008
Data Sheet DS1006
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
■ High Logic Density for System Integration
• 6K to 95K LUTs
• 90 to 583 I/Os
■ Embedded SERDES (LatticeECP2M Only)
• Data Rates 250 Mbps to 3.125 Gbps
• Up to 16 channels per device
PCI Express, Ethernet (1GbE, SGMII), OBSAI,
CPRI and Serial RapidIO.
■ sysDSP™ Block
• 3 to 42 blocks for high performance multiply and
accumulate
• Each block supports
– One 36x36, four 18X18 or eight 9X9 multipliers
■ Flexible Memory Resources
• 55Kbits to 5308Kbits sysMEM™ Embedded
Block RAM (EBR)
– 18Kbit block
– Single, pseudo dual and true dual port
– Byte Enable Mode support
• 12K to 202Kbits distributed RAM
– Single port and pseudo dual port
■ sysCLOCK Analog PLLs and DLLs
• Two GPLLs and up to six SPLLs per device
– Clock multiply, divide, phase & delay adjust
– Dynamic PLL adjustment
• Two general purpose DLLs per device
■ Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• Source synchronous standards support
– SPI4.2, SFI4 (DDR Mode), XGMII
– High Speed ADC/DAC devices
• Dedicated DDR and DDR2 memory support
– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
• Dedicated DQS support
■ Programmable sysI/O™ Buffer Supports
Wide Range Of Interfaces
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 3/2/18 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
■ Flexible Device Configuration
• 1149.1 Boundary Scan compliant
• Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual boot images supported
• TransFR™ I/O for simple field updates
• Soft Error Detect macro embedded
■ Optional Bitstream Encryption
(LatticeECP2/M “S” Versions Only)
■ System Level Support
• ispTRACY™ internal logic analyzer capability
• On-chip oscillator for initialization & general use
• 1.2V power supply
Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection Guide
Device
ECP2-6
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
LUTs (K)
6
12
21
32
48
68
Distributed RAM (Kbits)
12
24
42
64
96
136
EBR SRAM (Kbits)
55
221
276
332
387
1032
EBR SRAM Blocks
3
12
15
18
21
60
sysDSP Blocks
3678
18
22
18x18 Multipliers
12
24
28
32
72
88
GPLL + SPLL + DLL
2+0+2
2+0+2
2+0+2
2+0+2
2+2+2
2+4+2
Maximum Available I/O
190
297
402
450
500
583
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm)
90
93
208-pin PQFP (28 x 28 mm)
131
131
256-ball fpBGA (17 x 17 mm)
190
193
193
484-ball fpBGA (23 x 23 mm)
297
331
331
339
672-ball fpBGA (27 x 27 mm)
402
450
500
500
900-ball fpBGA (31 x 31 mm)
583
LatticeECP2/M Family Data Sheet
Introduction


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