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PC48F4400P0UB0 数据表(PDF) 78 Page - Numonyx B.V |
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PC48F4400P0UB0 数据表(HTML) 78 Page - Numonyx B.V |
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78 / 102 page  Numonyx™ Wireless Flash Memory (W18) Datasheet November 2007 78 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) 14.0 Set Read Configuration Register The Set Read Configuration Register (RCR) command sets the burst order, frequency configuration, burst length, and other parameters. A two-bus cycle command sequence initiates this operation. The Read Configuration Register data is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set Read Configuration Register command is written along with the configuration data (on the address bus). This is followed by a second write that confirms the operation and again presents the Read Configuration Register data on the address bus. The Read Configuration Register data is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the applied VPP voltage. After executing this command, the device returns to read-array mode. The Read Configuration Register’s contents can be examined by writing the Read Identifier command and then reading location 05h. See Table 30 and Table 31. Table 30: Read Configuration Register Summary First Access Latency Count Burst Length RM R LC2 LC1 LC0 WT DOC WC BS CC R R BW BL2 BL1 BL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 31: Read Configuration Register Descriptions (Sheet 1 of 2) Bit Name Description1 Notes 15 RM Read Mode 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) 2 14 R Reserved 5 13-11 LC[2:0] First Access Latency Count 001 = Reserved 010 = Code 2 011 = Code 3 100 = Code 4 101 = Code 5 111 = Reserved (Default) 6 10 WT WAIT Signal Polarity 0 = WAIT signal is asserted low 1 = WAIT signal is asserted high (Default) 3 9 DOC Data Output Configuration 0 = Hold Data for One Clock 1 = Hold Data for Two Clock (Default) 6 8 WC WAIT Configuration 0 = WAIT Asserted During Delay 1 = WAIT Asserted One Data Cycle before Delay (Default) 6 7 BS Burst Sequence 1 = Linear Burst Order (Default) 6 CC Clock Configuration 0 = Burst Starts and Data Output on Falling Clock Edge 1 = Burst Starts and Data Output on Rising Clock Edge (Default) 5R Reserved 5 4R Reserved 5 |
类似零件编号 - PC48F4400P0UB0 |
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类似说明 - PC48F4400P0UB0 |
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