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PC48F4400P0Y00 数据表(PDF) 20 Page - Numonyx B.V |
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PC48F4400P0Y00 数据表(HTML) 20 Page - Numonyx B.V |
20 / 102 page Numonyx™ Wireless Flash Memory (W18) Datasheet November 2007 20 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) WAIT Output WAIT: Output signal. Indicates invalid data during synchronous array or non-array flash reads. Read Configuration Register bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is deasserted; WAIT is not gated by F-OE#. • In synchronous array or non-array flash read modes, WAIT indicates invalid data when asserted and valid data when deasserted. • In asynchronous flash page read, and all flash write modes, WAIT is asserted. F-WP# Input FLASH WRITE PROTECT: Low-true input. F-WP# enables/disables the lock-down protection mechanism of the selected flash die. • F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked with software commands. • F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. ADV# Input ADDRESS VALID: Low-true input. During synchronous flash read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous flash read operations, addresses are latched on the rising edge of ADV#, or are continuously flow-through when ADV# is kept asserted. R-UB# R-LB# Input RAM UPPER / LOWER BYTE ENABLES: Low-true input. During RAM read and write cycles, R-UB# low enables the RAM high order bytes on D[15:8], and R- LB# low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die and are RFU on flash-only stacked combinations. F-RST# Input FLASH RESET: Low-true input. F-RST# low initializes flash internal circuitry and disables flash operations. F-RST# high enables flash operation. Exit from reset places the flash in asynchronous read array mode. P-Mode, P-CRE Input P-Mode (PSRAM Mode): Low-true input. P-Mode is used to program the Configuration Register, and enter/exit Low Power Mode of PSRAM die. P-Mode is available on stacked combinations with asynchronous-only PSRAM die. P-CRE (PSRAM Configuration Register Enable): High-true input. P-CRE is high, write operations load the refresh control register or bus control register. P-CRE is applicable only on combinations with synchronous PSRAM die. P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die. F-VPP, F-VPEN Power FLASH PROGRAM AND ERASE POWER: Valid F-VPP voltage on this ball enables flash program/erase operations. Flash memory array contents cannot be altered when F-VPP(F-VPEN) < VPPLK (VPENLK). Erase / program operations at invalid F-VPP (F-VPEN) voltages should not be attempted. Refer to flash discrete product datasheet for additional details. F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products. F[2:1]-VCC Power FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2 and flash die #3. Write operations are inhibited when F-VCC < VLKO. Device operations at invalid F-VCC voltages should not be attempted. F2-VCC is available on stacked combinations with two or three flash dies, and is an RFU on stacked combinations with only one flash die. S-VCC Power SRAM POWER SUPPLY: Supplies power for SRAM operations. S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations without SRAM die. P-VCC Power PSRAM POWER SUPPLY: Supplies power for PSRAM operations. P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked combinations without PSRAM die. VCCQ Power DEVICE I/O POWER: Supply power for the device input and output buffers. VSS Power DEVICE GROUND: Connect to system ground. Do not float any VSS connection. RFU — RESERVED for FUTURE USE: Reserved for future device functionality/ enhancements. Contact Numonyx regarding the use of balls designated RFU. DU — DO NOT USE: Do not connect to any other signal, or power supply; must be left floating. Table 8: Signal Descriptions - QUAD+ Package (Sheet 2 of 2) |
类似零件编号 - PC48F4400P0Y00 |
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类似说明 - PC48F4400P0Y00 |
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