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PF38F5070M0U0B 数据表(PDF) 46 Page - Numonyx B.V |
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PF38F5070M0U0B 数据表(HTML) 46 Page - Numonyx B.V |
46 / 102 page Numonyx™ Wireless Flash Memory (W18) Datasheet November 2007 46 Order Number: 290701-18 Numonyx™ Wireless Flash Memory (W18) 8.0 Power and Reset Specifications Numonyx™ Wireless Flash Memory (W18) devices have a layered approach to power savings that can significantly reduce overall system power consumption. The APS feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the memory enters its standby mode, where current consumption is even lower. Asserting RST# provides current savings similar to standby mode. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 8.1 Active Power With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to Section 6.1, “DC Current Characteristics” on page 23, for ICC values. When the device is in “active” state, it consumes the most power from the system. Minimizing device active current therefore reduces system power consumption, especially in battery-powered applications. 8.2 Automatic Power Savings (APS) Automatic Power Saving (APS) provides low-power operation during a read’s active state. During APS mode, ICCAPS is the average current measured over any 5 ms time interval 5 µs after the following events happen: • There is no internal sense activity; • CE# is asserted; • The address lines are quiescent, and at VSSQ or VCCQ. OE# may be asserted during APS. 8.3 Standby Power With CE# at VIH and the device in read mode, the flash memory is in standby mode, which disables most device circuitry and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or program operations, the device continues the operation and consumes corresponding active power until the operation is complete. ICCS is the average current measured over any 5 ms time interval 5 µs after a CE# de- assertion. 8.4 Power-Up/Down Characteristics The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; so it doesn’t matter whether VPP or VCC powers-up first. If VCCQ and/or VPP are not connected to the system supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCCMIN. Power supply transitions should only occur when RST# is low. 8.4.1 System Reset and RST# The use of RST# during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization |
类似零件编号 - PF38F5070M0U0B |
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类似说明 - PF38F5070M0U0B |
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