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AT87C5103-IBSIL 数据表(PDF) 5 Page - ATMEL Corporation |
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AT87C5103-IBSIL 数据表(HTML) 5 Page - ATMEL Corporation |
5 / 64 page 5 4134B–8051–06/03 Clock The Errata Sheet core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. Description The clock for the whole circuit and peripheral is first divided by 2 before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. The X2 bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 2 shows the mode switching waveforms. |
类似零件编号 - AT87C5103-IBSIL |
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类似说明 - AT87C5103-IBSIL |
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