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ST6373 数据表(PDF) 6 Page - STMicroelectronics |
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ST6373 数据表(HTML) 6 Page - STMicroelectronics |
6 / 64 page ST6373 6/64 1.2 PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection. OSCin, OSCout. These pins are internally con- nected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the cor- rect operation of the MCU with various stabili- ty/cost trade-offs. The OSCin pin is the input pin, the OSCout pin is the output pin. RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be dis- abled when the RESET pin is low to reduce power consumption during reset phase. TEST. The TEST pin must be held at VSS for nor- mal operation. PA0, PA1, PA2/HSYNCO, PA3/VSYNCO, PA4/CLMPO, PA5/BLKO, PA6/SCLI, PA7/SDAI – Port A. Software configurable as push-pull out- put, open-drain output, Schmitt trigger input with or without pull-up. Port A inputs can be also ORed into the INT1 interrupt. Port A outputs have a LED drive capability (10 mA). Pins PA2 and PA3 can be configured respectively as HSYNC and VSYNC outputs.Pins PA4 and PA5 can be configured respectively as CLAMP and BLANK Outputs.Pins PA6 and PA7 can be con- figurated as the I2C SPI pins SCLI and SDAI.The push-pull output and the input pull-up options do not exist for these two pins. After reset the PA0 to PA5 pins are configured as inputs with pull-up. PB0/AD0, PB1/AD1, PB2/AD2, PB3/AD3, PB4/AD4, PB5/AD5/HFLY, PB6/AD6/VFLY, PB7/AD7 – Port B. Each pin can be software configured as push-pull output, open-drain output, Schmitt trig- ger input with or without pull-up.Port B inputs can be also ored into the INT1 interrupt. Pins PB5 and PB6 can be configured as HFLY and VFLY inputs. In addition, any pin of port B can be soft- ware selected as the Analog-to-Digital converter input. Only one pin should be selected at a time, otherwise a conflict would result. After reset the port B pins are configured as inputs with pull-up. PC0/SCLD, PC1/SDAD, PC2, PC3/EXTCLK, PC4/PWRIN, PC5, PC6/HSYNC, PC7/HDRIV – Port C. Software configurable as open-drain out- puts or Schmitt trigger inputs with or without pull- ups. When configured as outputs, pins PC0 to PC3 are configured as 5V open-drain. Pins PC4 to PC7 are configured as open-drain 12V; the in- put pull-up option does not exist for these four pins. Pins PC0, PC1 and PC3 can be configured as the DDC SPI pins SCLD, SDAD and EXTCLK. The input pull-up option does not exist for PC0 and PC1. Pins PC6 and PC7 can be configured as HSYNC and HDRIV inputs. After reset: PC3 is configured as input with pull-up. PC0, PC1 & PC4 to PC7 are configured in input without pull- up. PC2 is in output mode with the value 1 (high impedance). DA0-DA8. These pins are the nine PWM D/A out- puts of the on-chip D/A converters. These lines have push-pull outputs with 5V drive. The output repetition rate is 31.25KHz (with 8MHz clock). VSYNC. This is the Vertical Synchronization pin. This pin is connected to an internal interrupt and is configured as input with pull-up and Schmitt trig- ger. HDA. This is the output pin of the on-chip 14-bit PWM D/A Converter. This line is a push-pull out- put with standard drive. NMI. This pin is the Non-Maskable interrupt input and is configured as input with pull-up and Schmitt trigger. Figure 2. ST6373 Pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 O0/DA0 O1/DA1 O2/DA2 O3/DA3 AD0/PB0 AD1/PB1 AD2/PB2 AD3/PB3 AD4/PB4 HFLY/AD5/PB5 VFLY/AD6/PB6 AD7/PB7 PA0 PA1 HSYNCO/PA2 VSYNCO/PA3 CLMPO/PA4 BLKO/PA5 SCLI/PA6 SDAI/PA7 VSS VDD PC0/SCLD PC1/SDAD PC2 PC3/EXTCLK PC4/PWRIN PC5 PC7/HDRIV HDA RESET OSCout OSCin TEST/V PP (1) VSYNC NMI DA4/O4 DAR/O5 DA6/O6 DA7/O7 DA8/O8 PC6/HSYNC (1) This pin is also the VPP input for OTP/EPROM devices |
类似零件编号 - ST6373 |
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类似说明 - ST6373 |
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