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ST5451D 数据表(PDF) 11 Page - STMicroelectronics |
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ST5451D 数据表(HTML) 11 Page - STMicroelectronics |
11 / 34 page CD Configuration Register D After reset 00 Content of CD indicate TEI z value. 7 High Order Bits TEI 0 CE Configuration Register E After reset 00 Content of CE indicate TEI t value. 7 High Order Bits TEI 0 CF Configuration Register F After 00 TE MAS/SSC CCS CMS/SC PI VZDOUT MDS1 MDS0 TE TE mode TE = 1 : the frame is constitued by three GCI channels (GCI-SCIT) MAS/SSC If CCS = 0, TE = 1, MDS0 and MDS1 = 1 (i.e. GCI mode, TE mode, 16 Kbit/s) MAS/SSc is MAS and: MAS = 0 means ”Slave device” MAS = 1 means ”Master device” If SC = 1 (i.e. a sub-channel is se- lected) MAS/SSC is SSC; if 16Kb is se- lected SSC chooses between first on second bit of the stream while, if 64Kb is selected SSC chooses between first or last seven bits of the stream (see TABLE 2 and CMS/SC) CCS Channel Capacity Selection CCS = 1: 64 Kb/s CCS = 0: 16 Kb/s. CMS/SC If CCS = 0, TE = 1, MDS0 and MDS1 = 1 (i.e. GCI mode, TE mode, 16Kbit/s) CMS/SC is CMS (Contention mode se- lection) and: CMS = 1 means ”D and C/I channel access procedure active” CMS = 0 means ”D and C/Z channel access procedure active” If CCS = 1 and TE = 1 CMS/SC is SC (Subchannel) and: SC = 0 means ”16Kbit/s or 64Kbit/s is used” SC = 1 means ”an 8Kbit/s or 56Kbit/s subchannel inside a 16Kbit/s or 64kbit/sis used” (see MAS/SSC) PI Peripheral Interface (only if TE=1) PI = 1: CIX2, CIR2, MONX2, MONR2, active VZDOUT When level 1 device is inactive (i.e. CIR1 = DI = 1111) and GCI has to be waken up (i.e. TIM = 0000 in CIX1), DOUT is set to zero requiring FS and CLK if VZ DOUT=1. MDS1 Mode Bit 1 MDS1 = 1:GCI mode MDS1 = 0: Multiplexed mode MDS0 Mode Bit 0 MDS0 = 1: Multiplexer and Demulti- plexer are active. MDS=0 No multiplexer. CCR Configuration Register 00 After reset 00 TLP ADDR AD3 AD2 AD1 AD0 CRS TRI TLP Test Loop TLP = 1: The transmitter is internally connected to the receiver; the transmit output is not activated. The digital inter- face must be activated to provide the bit clock and frame Synchro. ADDR Address Recognized If TE = 1 and PI = 1 ADDR = 1: The first byte received in MONR2 is compared with AD0/3. If equal the message is accepted, other- wise is ignored. ADDR = 0: The message is always ac- cepted. AD0/3 When PI = 1, is the component ad- dress. AD0/2 Address bit used to access D and C/I channels (TE = CMS =1, CCS = 0). CRS Clock Rate Selection CRS = 1: Clock frequency is twice the data rate (GCI). CRS = 0: Clock frequency and data rate are identical. TRI Tristate TRI = 1: DOUT in tristate TRI = 0: DOUT in open drain. ST5451 11/34 |
类似零件编号 - ST5451D |
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类似说明 - ST5451D |
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