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LTC1860CMS8 数据表(PDF) 7 Page - Linear Technology |
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LTC1860CMS8 数据表(HTML) 7 Page - Linear Technology |
7 / 12 page 7 LTC1860/LTC1861 18601f CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin. LTC1861 (SO-8 Package) LTC1861 (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input de- fines the span of the A/D converter and must be kept free of noise with respect to AGND. PI FU CTIO S FUNCTIONAL BLOCK DIAGRA 1860/61 BD 12-BIT SAMPLING ADC BIAS AND SHUTDOWN CONVERT CLK SERIAL PORT 12-BITS IN+ (CH0) IN– (CH1) VCC VREF SDO GND CONV (SDI) SCK PIN NAMES IN PARENTHESES REFER TO LTC1861 DATA OUT DATA IN + – |
类似零件编号 - LTC1860CMS8 |
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类似说明 - LTC1860CMS8 |
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