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EM78P342NP 数据表(PDF) 39 Page - ELAN Microelectronics Corp |
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EM78P342NP 数据表(HTML) 39 Page - ELAN Microelectronics Corp |
39 / 102 page EM78P341N/342N/343N 8-Bit Microprocessor with OTP ROM Product Specification (V1.0) 12.01.2006 • 33 (This specification is subject to change without further notice) 6.4 I/O Ports The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain output set through software. Port 5 features an input status changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are illustrated in Figures 6-4, 6-5, 6-6, & 6-7 (see next page). PCWR PCRD PDWR PDRD IOD 0 1 M U X PORT Q Q _ D D Q Q _ CLK P R C L CLK P R C L Note: Open-drain is not shown in the figure. Fig. 6-4 I/O Port and I/O Control Register Circuit for Port 6 and Port 7 PCRD IOD PCWR PDWR PDRD Bit 6 of IOCE PORT M U X 0 1 CLK CLK CLK P P P R R R C L L L C C Q Q Q Q Q Q D D D _ _ _ INT Note: Open-drain is not shown in the figure. Fig. 6-5 I/O Port and I/O Control Register Circuit for P60 (/INT) |
类似零件编号 - EM78P342NP |
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类似说明 - EM78P342NP |
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