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21152 数据表(PDF) 92 Page - Intel Corporation

部件名 21152
功能描述  PCI-to-PCI Bridge
Download  148 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

21152 数据表(HTML) 92 Page - Intel Corporation

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21152 PCI-to-PCI Bridge Preliminary Datasheet
Exclusive Access
When the locked delayed read request transaction moves to the head of the delayed transaction
queue, the 21152 initiates the transaction as a locked read transaction by deasserting s_lock_l on
the secondary bus during the first address phase, and by asserting s_lock_l one cycle later. If
s_lock_l is already asserted (used by another initiator), the 21152 waits to request access to the
secondary bus until s_lock_l is sampled deasserted when the secondary bus is idle. Note that the
existing lock on the secondary bus could not have crossed the 21152; otherwise, the pending
queued locked transaction would not have been queued. When the 21152 is able to complete a data
transfer with the locked read transaction, the lock is established on the secondary bus.
When the initiator repeats the locked read transaction on the primary bus with the same address,
transaction type, and byte enable bits, the 21152 transfers the read data back to the initiator, and the
lock is then also established on the primary bus.
For the 21152 to recognize and respond to the initiator, the initiator’s subsequent attempts of the
read transaction must use the locked transaction sequence (deassert p_lock_l during address phase,
and assert p_lock_l one cycle later). If the LOCK# sequence is not used in subsequent attempts, a
master time-out condition may result. When a master time-out condition occurs, p_serr_l is
conditionally asserted (see Section 7.4), the read data and queued read transaction are discarded,
and the s_lock_l signal is deasserted on the secondary bus.
Once the intended target has been locked, any subsequent locked transactions initiated on the primary
bus that are forwarded by the 21152 are driven as locked transactions on the secondary bus.
When the 21152 receives a target abort or a master abort in response to the delayed locked read
transaction, this status is passed back to the initiator, and no locks are established on either the
target or the initiator bus. The 21152 resumes forwarding unlocked transactions in both directions.
When the 21152 detects, on the secondary bus, a locked delayed transaction request intended for a
target on the primary bus, the 21152 queues and forwards the transaction as an unlocked
transaction. The 21152 ignores s_lock_l for upstream transactions and initiates all upstream
transactions as unlocked transactions.


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