Metal Oxide Varistors

CA04P2S14THSG

SMD Multilayer Varistor Array with Ni-Barrier Termination

B72762A8140S160

Preliminary data sheet

(parameters may be changed if necessary)

ISSUE DATE

08.07.02

ISSUE

c

PUBLISHER

KB VS PE

PAGE

1/7

Designation System

CA

= Chip Array

04

= Dimensions of the device 04x05 (Length x width in 1/100 inch)

P

= Design (Parallel internal structure)

2

= Number of elements

S

= Special Tolerance of the varistor voltage

14

= Max. operating voltage

T= Three layer termination (Ni-barrier)

HS

= Designed for protection of High Speed data lines

G

= Taped version, cardboard tape, 7" reel (5000 pcs/reel)

Figure

l =

1,37 ± 0,15

b = 1,0 + 0/ -0,15

s = 0,70 max.

d = 0,36 ± 0,1

(All dimensions in mm)

As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for

applications, processes and circuits implemented within components or assemblies. The information describes the type of

component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.

e

d

s

b

l