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21150 数据表(PDF) 51 Page - Intel Corporation |
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21150 数据表(HTML) 51 Page - Intel Corporation |
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51 / 164 page  21150 Preliminary Datasheet 43 In addition to accepting configuration transactions for initialization of its own configuration space, the 21150 also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest 2 bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest 2 address bits set to 01b. Figure 12 shows the address formats for Type 0 and Type 1 configuration transactions. The register number is found in both Type 0 and Type 1 formats and gives the Dword address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single- function devices, this value is not decoded. Type 1 configuration transaction addresses also include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. 4.7.1 Type 0 Access to the 21150 The 21150 configuration space is accessed by a Type 0 configuration transaction on the primary interface. The 21150 configuration space cannot be accessed from the secondary bus. The 21150 responds to a Type 0 configuration transaction by asserting p_devsel_l when the following conditions are met during the address phase: • The bus command is a configuration read or configuration write transaction. • Low 2 address bits p_ad<1:0> must be 00b. • Signal p_idsel must be asserted. The function code is ignored because the 21150 is a single-function device. Figure 12. Configuration Transaction Address Formats LJ-04638.A14 31 24 23 16 Device Number Func. No. Register No. 0 1 Bus Number Func. No. Register No. 0 0 Reserved Reserved Type 1 15 11 10 08 07 02 01 00 31 Type 0 11 10 08 07 02 01 00 |
类似零件编号 - 21150 |
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类似说明 - 21150 |
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