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ADSP-21266SKSTZ-1C 数据表(PDF) 5 Page - Analog Devices |
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ADSP-21266SKSTZ-1C 数据表(HTML) 5 Page - Analog Devices |
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5 / 44 page  ADSP-21266 Rev. C | Page 5 of 44 | October 2007 Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele- ments. These computation units support IEEE 32-bit single precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2126x enhanced Har- vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21266 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro- gram memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With the ADSP-21266’s separate pro- gram and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-21266 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-21266’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Figure 2. ADSP-21266 System Sample Configuration DAI SPORT5 SPO RT4 SPORT3 SPO RT2 SP ORT1 SPORT0 SCLK0 SD0A SFS0 SD0B SRU DAI_ P1 DAI_P 2 DAI_P 3 DAI_ P1 8 DAI_ P19 DAI_P 20 DAC (OP TIONAL) ADC (OPTI ONAL) FS CLK SDAT FS CLK SDAT 3 CLOCK 2 2 CLKI N XTAL CLK_ CFG 1– 0 BOOTCFG1– 0 FLAG 3– 1 ADDR PARALLE L PO RT RAM , ROM BOOT ROM I/O DEVICE OE DATA WE RD WR CLKOUT ALE AD15 –0 LATCH RESE T JTAG 6 ADS P-21266 CS FLAG0 PCGB PCG A CLK FS |
类似零件编号 - ADSP-21266SKSTZ-1C |
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类似说明 - ADSP-21266SKSTZ-1C |
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