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STA328 数据表(PDF) 6 Page - STMicroelectronics |
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STA328 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 57 page  Description STA328 6/57 1.2 EQ processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In this block, up to four user-defined biquads can be applied to each of the two channels. Pre-scaling, DC-blocking, high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings. The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. And the CxEQBP bits can be used to bypass the EQ function on a per channel basis. Figure 3 shows the internal signal flow through the EQ block. Figure 3. Channel signal flow through the EQ block 1.3 Output configurations Figure 4. Output power-stage configurations Pre Scale High-Pass Filter BQ#1 BQ#2 Bass Filter De- Emphasis Treble Filter Re-sampled Input To Mix BQ#4 BQ#3 If HPB = 0 4 Biquads User defined if AMEQ = 00 Preset EQ if AMEQ = 01 Auto Loudness if AMEQ = 10 If DEMP = 1 If CxT CB = 0 BT C: Bass Boost/Cut T T C: T reble Boost/Cut If DSPB = 0 & CxEQB = 0 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 2 Channel 1 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 2 Channel 1 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 Channel 1 Channel 2 2-channel (full-bridge) configuration, register bits OCFG[1:0] = 00 2.1-channel configuration, register bits OCFG[1:0] = 01 1-channel mono-parallel configuration, register bits OCFG[1:0] = 11 The setup register is Configuration register F (addr 0x05) on page 31 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 |
类似零件编号 - STA328 |
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类似说明 - STA328 |
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