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STP2223BGA
UPA to PCI Interface
U2P
July 1997
PRODUCT SUMMARY
The U2P uses the standard cell library from Lucent Technologies. It is implemented in 0.35 micron, 3 level
metal and 3.3 volt optimized CMOS technology.
The U2P die has 352 signal pads (including specialty power/grounds) and 104 VSS/VDD pads for a total pad
count of 456. The U2P package is a 456 pin PBGA, with 352 signal pins and 104 VSS/VDD pins. Its die con-
sists of 170k gates and 29k bits of RAM.
The U2P design includes the following non-standard cells:
• 5V tolerant PCI pads.
• 66MHz capable PCI pads.
• UPA pads (without holding amps).
• PLL and PECL receiver for UPA clock.
• PLL for main clock.
The UPA operation is up to 100 MHz (10ns). Its main internal clock is up to 66.7 MHz (15 ns). The PCI bus A
clocks at 1x or 0.5x internal clock (synchronous). The PCI bus B clocks at 0.5x internal clock (synchronous).
The maximum power consumption is 3 watts.