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22CV10AZ-25 Datasheet(数据表) 3 Page - List of Unclassifed Manufacturers

部件型号  22CV10AZ-25
说明  CMOS Programmable Electrically Erasable Logic Device
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

22CV10AZ-25 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

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PEEL™ 22CV10AZ
Function Description
The implements logic functions as sum-of-products expres-
sions in a programmable-AND/fixed-OR logic array. User-
defined functions are created by programming the connec-
tions of input signals into the array. User-configurable out-
put structures in the form of I/O macrocells further increase
logic flexibility.
Architecture Overview
The architecture is illustrated in the block diagram of Figure
19. Twelve dedicated inputs and 10 I/Os provide up to 22
inputs and 10 outputs for creating logic functions (see Fig-
ure 21). At the core of the device is a programmable electri-
cally-erasable AND array that drives a fixed OR array. With
this structure, the PEEL™22CV10AZ can implement up to
10 sum-of-products logic expressions.
Associated with each of the ten OR functions is an I/O mac-
rocell that can be independently programmed to one of four
different configurations in standard 22V10 mode, or any
one of 12 configurations using the special “Plus” mode. The
programmable macrocells allow each I/O to be used to cre-
ate sequential or combinatorial logic functions of active-
high or active-low polarity, while providing three different
feedback paths into the AND array.
AND/OR Logic Array
The programmable AND array of the PEEL™22CV10AZ
(shown in Figure 21) is formed by input lines intersecting
product terms. The input lines and product terms are used
as follows:
s
44 Input Lines:
– 24 input lines carry the true and complement of the
signals applied to the 12 input pins
– 20 additional lines carry the true and complement
values of feedback or input signals from the 10 I/Os
s
133 Product Terms:
– 120 product terms (arranged in 2 groups of 8, 10, 12,
14, and 16) are used to form sum of product functions
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
that is connected to both the true and complement of an
input signal will always be FALSE and therefore will not
affect the OR function that it drives. When all the connec-
tions on a product term are opened, a “don’t care” state
exists and that term will always be TRUE.
When programming the PEEL™22CV10AZ, the device
programmer first performs a bulk erase to remove the previ-
ous pattern. The erase cycle opens every logical connec-
tion in the array. The device is configured to perform the
user-defined function by programming selected connec-
tions in the AND array. (Note that PEEL™ device program-
mers automatically program all of the connections on
unused product terms so that they will have no effect on the
output function).
Variable Product Term Distribution
The PEEL™22CV10AZ provides 120 product terms to
drive the 10 OR functions. These product terms are distrib-
uted among the outputs in groups of 8, 10, 12, 14, and 16
to form logical sums (see Figure 21). This distribution
allows optimum use of the device resources.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides
complete control over the architecture of each output. The
ability to configure each output independently lets you to
tailor the configuration of the PEEL™22CV10AZ to the pre-
cise requirements of your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 20, consists of a D-
type flip-flop and two signal-select multiplexers. The config-
uration of the macrocell is determined by four EEPROM
bits that control the multiplexers. These bits determine the
output polarity, output type (registered or non-registered)
and input-feedback path (bidirectional I/O, combinatorial
feedback). Refer to Table 1. for details. Four of these mac-
rocells duplicate the functionality of the industry-standard
PAL22V10. (See Figure 21 and Table 1.)
Figure 20 Block Diagram of the
PEEL™22CV10A I/O Macrocell




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