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UC37136DP 数据表(PDF) 3 Page - Texas Instruments |
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UC37136DP 数据表(HTML) 3 Page - Texas Instruments |
3 / 9 page UC27136, UC37136 DUAL OUTPUT SWITCH SLUS447 - FEBRUARY 2000 - REVISED JULY 2000 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics VCC = 25 V, IN1 = IN2 = INV2 = 0 V (for low), IN1 = IN2 = INV2 = 5 V (for high), TA = TJ, CDEL = 10 nF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output: Low Side Configuration Section Rise time (on to off) RLOAD = 250 Ω, See Figure 2 300 ns Fall Time (off to on) RLOAD = 250 Ω, See Figure 2 150 ns Saturation voltage RLOAD = 100 Ω,TA = 25°C, See Figure 2 1.15 V Sa u a o o age RLOAD = 100 Ω,TA = –40°C, See Figure 2 1.3 V Current limit RLOAD = 0.25 Ω,TA = 25°C, See Figure 2 1.1 A Leakage current HS1, HS2 = GND, LS1, LS2 = VCC, IN1, IN2, INV2 = 0 V 5 µA Voltage clamp Measure (VLS1 - VHS1) or (VLS2 - VHS2) 46 V Turn On Delay CDEL maximum voltage 4.7 V CDEL threshold 4 V ICDEL 2.5 µA Thermal Shutdown (see Note 1) Thermal shutdown threshold 155 °C Hysteresis 20 °C NOTE 1: Ensured by design. Not production tested. pin descriptions CDEL: A capacitor connected to this pin is used to program a turnon delay after the UVLO threshold has been reached. The UVLO function keeps the external capacitor connected to this pin discharged until VCC is greater than 8 V. After the UVLO upper trip point of 8 V has been exceeded, an internal 2.5- µA current source charges the capacitor from GND to 4.7 V. An internal voltage comparator enables the output NPN switches at 4 V, imparting a time delay after UVLO. As an added feature, an external switch can be connected in parallel with the user-programmable time-delay capacitor to disable the output NPN switches and reset the time delay capacitor by external means. GND: The reference point for the internal reference, all thresholds, and the ground for the remainder of the device. IN1: The digital-logic input pin that controls the state of the output NPN switch 1. When the IN1 pin is a logic low (0 V to 1.5 V), output switch 1 is off (non-conducting). When the IN1 pin is a logic high (3.5 V to 17.5 V), output switch 1 is on (conducting). IN2, INV2: The digital logic input pins to the exclusive OR gate that controls the state of the output NPN switch 2. Refer to the truth table for description. A logic low is 0 V to 1.5 V; a logic high is 3.5 V to 17.5 V. HS1: This pin is the emitter of output NPN switch 1. HS2: This pin is the emitter of output NPN switch 2. LS1: This pin is the collector of output NPN switch 1. LS2: This pin is the collector of output NPN switch 2. SD: This ground referenced open collector NPN output is asserted in the event of an overcurrent or during the start up delay due to the CDEL pin, non-conducting otherwise. The maximum SD current is 8 mA. |
类似零件编号 - UC37136DP |
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类似说明 - UC37136DP |
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