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AD7352 数据表(PDF) 11 Page - Analog Devices

部件名 AD7352
功能描述  Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7352 数据表(HTML) 11 Page - Analog Devices

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Preliminary Technical Data
AD7357
Rev. PrD | Page 11 of 17
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7357 is a fast, dual, 14-bit, single-supply, successive
approximation analog-to-digital converter. The part operates
from a 2.5 V power supply and features throughput rates up to
4.25 MSPS.
The AD7357 contains two on-chip differential track-and-hold
amplifiers, two successive approximation analog-to-digital
converters and a serial interface with two separate data output
pins. They part is housed in a 16-lead TSSOP package, offering
the user considerable space-saving advantages over alternative
solutions.
The serial clock input accesses data from the part, but also
provides the clock source for each successive approximation
ADC. The AD7357 has an on-chip 2.048V reference. If an
external reference is desired the internal reference can be
overdriven with a reference of value ranging from (2.048V +
100mV) to Vdd. If the internal reference is to be used elsewhere
in the system, then the reference output needs to be buffered
first. The differential analog input range for the AD7357 is VCM
± VREF∕2.
The AD7357 features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7357 has two successive approximation analog-to-
digital converters, each based around two capacitive DACs.
Figure 8 and Figure 9 show simplified schematics of one of
these ADCs in acquisition and conversion phase, respectively.
The ADC is comprised of control logic, a SAR, and two
capacitive DACs. In Figure 8 (the acquisition phase), SW3 is
closed, SW1 and SW2 are in position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays may
acquire the differential signal on the input.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
CS
CS
VIN+
VIN–
VREF
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion (Figure 9), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the VIN+ and VIN- pins must be matched,
otherwise, the two inputs will have different settling times,
resulting in errors.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
CS
CS
VIN+
VIN–
VREF
Figure 9. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7357 is straight binary. The
designed code transitions occur at successive LSB values (1 LSB,
2 LSBs and so on). The LSB size is (2 ×VREF)/16384 for the
AD7357. The ideal transfer characteristic of the AD7357 is
shown in Figure 10.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+VREF–1.5 LSB
+VREF–1 LSB
–VREF+1 LSB
–VREF+0.5 LSB
Figure 10. AD7356 Ideal Transfer Characteristic
ANALOG INPUT STRUCTURE
Figure 11 shows the equivalent circuit of the analog input
structure of the AD7357. The four diodes provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300mV. This causes these diodes to become forward-
biased and start conducting into the substrate. These diodes can


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