数据搜索系统,热门电子元器件搜索 |
|
AD9879BSZ 数据表(PDF) 6 Page - Analog Devices |
|
AD9879BSZ 数据表(HTML) 6 Page - Analog Devices |
6 / 32 page AD9879 Rev. A | Page 6 of 32 Parameter Temp Test Level Min Typ Max Unit Signal-to-Noise Ratio (SNR) Full II 46.2 57.2 Bits Total Harmonic Distortion (THD) Full II −50.1 −44.5 dB Spurious-Free Dynamic Range (SFDR) Full II 44.9 53.4 dB CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (AOUT = 5 MHz) Isolation Between Tx and IQ ADCs 25°C III >60 dB Isolation Between Tx and 10-Bit ADC 25°C III >80 dB Isolation Between Tx and 12-Bit ADC 25°C III >80 dB ADC-to-ADC (AIN = –0.5 dBFS, f = 5 MHz) Isolation Between IF10 and IF12 ADCs 25°C III >85 dB Isolation Between Q and I Inputs 25°C III >50 dB TIMING CHARACTERISTICS (10 pF Load) Minimum RESET Pulse Width Low (tRL) N/A N/A 5 tMCLK cycles Digital Output Rise/Fall Time Full II 2.8 4 ns Tx/Rx Interface MCLK Frequency (fMCLK) Full II 66 MHz TxSYNC/TxIQ Setup Time (tSU) Full II 3 ns TxSYNC/TxIQ Hold Time (tHD) Full II 3 ns MCLK Rising Edge to RxSYNC/RxIQ/IF Valid Delay (tMD) Full II 0 1.0 ns REFCLK Rising or Falling Edge to RxSYNC/RxIQ/IF Valid Delay (tOD) Full II TOSC/4 – 2.0 TOSC/4 + 3.0 ns REFCLK Edge to MCLK Falling Edge (tEE) Full II −1.0 +1.0 ns Serial Control Bus Maximum SCLK Frequency (fSCLK) Full II 15 MHz Minimum Clock Pulse Width High (tPWH) Full II 30 ns Minimum Clock Pulse Width Low (tPWL) Full II 30 ns Maximum Clock Rise/Fall Time Full II 1 ms Minimum Data/Chip-Select Setup Time (tDS) Full II 25 ns Minimum Data Hold Time (tDH) Full II 0 ns Maximum Data Valid Time (tDV) Full II 30 ns CMOS LOGIC INPUTS Logic 1 Voltage 25°C II VDRVDD – 0.7 V Logic 0 Voltage 25°C II 0.4 V Logic 1 Current 25°C II 12 µA Logic 0 Current 25°C II 12 µA Input Capacitance 25°C II 3 pF CMOS LOGIC OUTPUTS (1 mA Load) Logic 1 Voltage 25°C II VDRVDD – 0.6 V Logic 0 Voltage 25°C II 0.4 V POWER SUPPLY Supply Current, IS (Full Operation) 25°C II 163 184 mA Analog Supply Current, IAS 25°C III 95 mA Digital Supply Current, IDS 25°C III 68 mA Supply Current, IS Standby (PWRDN Pin Active) 25°C II 119 126 mA Full Power-Down (Register 0x02 = 0xF9) 25°C III 16 mA Power-Down Tx Path (Register 0x02 = 0x60) 25°C III 113 mA Power-Down Rx Path (Register 0x02 = 0x19) 25°C III 110 mA 1 IQ ADC in default mode. ADC Clock Select Register 8, Bit 3 set to 0. |
类似零件编号 - AD9879BSZ |
|
类似说明 - AD9879BSZ |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |