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LM2651MTCX-ADJ 数据表(PDF) 10 Page - National Semiconductor (TI) |
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LM2651MTCX-ADJ 数据表(HTML) 10 Page - National Semiconductor (TI) |
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10 / 11 page  Design Procedure (Continued) EXTERNAL SCHOTTKY DIODE A Schottky diode D 1 is recommended to prevent the intrinsic body diode of the low-side MOSFET from conducting during the deadtime in PWM operation and hysteretic mode when both MOSFETs are off. If the body diode turns on, there is extra power dissipation in the body diode because of the reverse-recovery current and higher forward voltage; the high-side MOSFET also has more switching loss since the negative diode reverse-recovery current appears as the high-side MOSFET turn-on current in addition to the load current. These losses degrade the efficiency by 1-2%. The improved efficiency and noise immunity with the Schottky diode become more obvious with increasing input voltage and load current. The breakdown voltage rating of D 1 is preferred to be 25% higher than the maximum input voltage. Since D 1 is only on for a short period of time, the average current rating for D 1 only requires being higher than 30% of the maximum output current. It is important to place D 1 very close to the drain and source of the low-side MOSFET, extra parasitic inductance in the parallel loop will slow the turn-on of D 1 and direct the current through the body diode of the low-side MOSFET. When an undervoltage situation occurs, the output voltage can be pulled below ground as the inductor current is re- versed through the synchronous FET. For applications which need to be protected from a negative voltage, a clamping diode D2 is recommended. When used, D2 should be con- nected cathode to V OUT and anode to ground. A diode rated for a minimum of 2A is recommended. PCB Layout Considerations Layout is critical to reduce noises and ensure specified performance. The important guidelines are listed as follows: 1. Minimize the parasitic inductance in the loop of input capacitors and the internal MOSFETs by connecting the input capacitors to V IN and PGND pins with short and wide traces. This is important because the rapidly switching current, together with wiring inductance can generate large voltage spikes that may result in noise problems. 2. Minimize the trace from the center of the output resistor divider to the FB pin and keep it away from noise sources to avoid noise pick up. For applications requir- ing tight regulation at the output, a dedicated sense trace (separated from the power trace) is recommended to connect the top of the resistor divider to the output. 3. If the Schottky diode D 1 is used, minimize the traces connecting D 1 to SW and PGND pins. 10092523 Schematic for the Typical Board Layout www.national.com 10 |
类似零件编号 - LM2651MTCX-ADJ |
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类似说明 - LM2651MTCX-ADJ |
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