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16CV8-25 Datasheet(数据表) 1 Page - List of Unclassifed Manufacturers

部件型号  16CV8-25
说明  CMOS Programmable Electrically Erasable Logic Device
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制造商  ETC2 [List of Unclassifed Manufacturers]
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16CV8-25 Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers

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1
04-02-004I
Commercial
The PEELTM 16CV8 architecture allows it to replace over standard 20-
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. ICT’s PEELTM 16CV8
can be programmed with existing 16CV8 JEDEC file. Some program-
mers also allow the PEELTM 16CV8 to be programmed directly from
PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development
and programming support for the PEELTM16CV8 is provided by popular
third-party programmers and development software. ICT also offers free
PLACE development software.
General Description
The PEELTM 16CV8 is a Programmable Electrically Erasable Logic
(PEEL) device providing an attractive alternative to ordinary PLDs. The
PEELTM 16CV8 offers the performance, flexibility, ease of design and
production practicality needed by logic designers today.
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as
low as 37mA. EE-Reprogrammability provides the convenience of
instant reprogramming for development and reusable production inven-
tory minimizing the impact of programming changes or errors. EE-
Reprogrammability also improves factory testability, thus assuring the
highest quality possible.
PEEL™ 16CV8 -25
CMOS Programmable Electrically Erasable Logic Device
Features
Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices
Figure 1 - Pin Configuration
DIP
I/CLK1
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
GND
10
11
I
12
I/O
V
CC
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
1
I/CLK1
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
GND
20
V
CC
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
TSSOP
12
I/O
11
I
1
I/CLK1
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
GND
20
V
CC
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
SOIC
12
I/O
11
I
4
I
5
I
6
I
7
I
8
I
9 10 11 12 13
3
2
1
19
PLCC-J
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
20
Figure 2 - Block Diagram
64 TERMS
X
32 INPUTS
PEEL
"AND"
ARRAY
CLK
MACRO
CELL
/CLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OE




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