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L9352 数据表(PDF) 6 Page - STMicroelectronics |
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L9352 数据表(HTML) 6 Page - STMicroelectronics |
6 / 21 page L9352 6/21 Additional Diagnostic Functions channel 3 and channel 4 (regulated channels) DCOUT Output duty cycle range filtered with 10ms 10 90 % IQO3,4 Overload current channel 3,4 VS ≥ 6.5V 2.5 5 8 A Vrerr Recirculation error shutdown threshold (open D3/D4) Iout > 50mA 45 50 60 V PWMdOU T Output PWM ratio during drift comparison VIN3 = VIN4 = PWMIN VTEST = H -14.3 +14.3 % Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90% VIL Input low voltage -0.3 1 V VIH Input high voltage 2 6 V VIHy Input voltage hysteresis(1) 20 500 mV II Input pull down current VIN = 5V, VS ≥ 6.5V 820 40 µA Digital Outputs (ST1 to ST4) VSTL Status output voltage in low state (2)) IST ≤ 40µA 0 0.4 V VSTH Status output voltage in high state (2) IST ≥ -40µA 2.5 3.45 V IST ≥ -120µA 23.45 V RDIAGL ROUT + RDSON in low state 0.3 0.64 1.5 k Ω RDIAGH ROUT + RDSON in high state 1.5 3.2 7.0 k Ω Power Outputs (Q1 to Q4) RDSON Static drain-source ON-resistance IQ = 1A; VS ≥ 9.5V 0.2 0.4 Ω VF_250mA Forward voltage of free wheeling path D3, D4 @250mA ID3/4 = -250mA 0.5 1.5 V VF_2.25A Forward voltage of free wheeling path D3, D4 @2.25A ID3/4 = -2.25A 2.0 4.5 V Rsens Sense resistor = (VF_2.25A-VF_250mA)/ 2A 1 Ω VZ Z-diode clamping voltage IQ ≥ 100mA 45 60 V IPD Output pull down current VEN = H, VIN = L 10 150 µA IQlk Output leakage current VEN = L; VQ = 20V 5 µA Timing tON Output ON delay time IQ = 1A 05 20 µs tOFF Output OFF delay time channel IQ = 1A 010 30 µs tOFFREG Output OFF delay time regulator (3) 528 µs tr Output rise time IQ = 1A 0.5 1.5 8 µs ELECTRICAL CHARACTERISTCS: (continued) (Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit |
类似零件编号 - L9352 |
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类似说明 - L9352 |
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