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ISL59530_0708 数据表(PDF) 6 Page - Intersil Corporation |
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ISL59530_0708 数据表(HTML) 6 Page - Intersil Corporation |
6 / 25 page 6 FN6220.6 August 29, 2007 - T19 OVER5 Overlay Logic Control (with pull-down) - P20 OVER6 Overlay Logic Control (with pull-down) - M20 OVER7 Overlay Logic Control (with pull-down) - K19 OVER8 Overlay Logic Control (with pull-down) - H19 OVER9 Overlay Logic Control (with pull-down) - F20 OVER10 Overlay Logic Control (with pull-down) - D20 OVER11 Overlay Logic Control (with pull-down) - B17 OVER12 Overlay Logic Control (with pull-down) - B15 OVER13 Overlay Logic Control (with pull-down) - A13 OVER14 Overlay Logic Control (with pull-down) - A11 OVER15 Overlay Logic Control (with pull-down) - V10 VOVER0 Overlay Video Input - V12 VOVER1 Overlay Video Input - V14 VOVER2 Overlay Video Input - V16 VOVER3 Overlay Video Input - V18 VOVER4 Overlay Video Input - T18 VOVER5 Overlay Video Input - P18 VOVER6 Overlay Video Input - M18 VOVER7 Overlay Video Input - K18 VOVER8 Overlay Video Input - H18 VOVER9 Overlay Video Input - F18 VOVER10 Overlay Video Input - D18 VOVER11 Overlay Video Input - C17 VOVER12 Overlay Video Input - C15 VOVER13 Overlay Video Input - C13 VOVER14 Overlay Video Input - C11 VOVER15 Overlay Video Input 22 M3 VREF DC-restore clamp reference input. In an AC-coupled configuration (DC-Restore clamp enabled), the sync tip of composite video inputs will be restored to this level. Set to 0.3V to 0.7V for optimum performance. In an DC-coupled configuration (DC-Restore clamp disabled), this pin should be tied to ground. Do not let the VREF pin float! A floating VREF pin drifts high and, if the clamp function is enabled, will cause all of the outputs to simultaneously try to drive ~4V DC into their 150 Ω loads. 9 J3 SLATCH Serial Latch. Serial data is latched into ISL59530 on rising edge of SLATCH. 11 K3 CLK Serial data clock 18 L3 SDI Serial data input Pin Descriptions (Continued) 72 LD QFN 356 LD BGA NAME DESCRIPTION ISL59530 |
类似零件编号 - ISL59530_0708 |
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类似说明 - ISL59530_0708 |
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