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DP83848H 数据表(PDF) 49 Page - National Semiconductor (TI) |
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DP83848H 数据表(HTML) 49 Page - National Semiconductor (TI) |
49 / 78 page 49 www.national.com 5 Jabber Detect 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register. 1 = Jabber condition detected. 0 = No Jabber. 4 Auto-Neg Complete 0, RO Auto-Negotiation Complete: 1 = Auto-Negotiation complete. 0 = Auto-Negotiation not complete. 3 Loopback Status 0, RO Loopback: 1 = Loopback enabled. 0 = Normal operation. 2 Duplex Status 0, RO Duplex: This bit indicates duplex status and is determined from Auto-Nego- tiation or Forced Modes. 1 = Full duplex mode. 0 = Half duplex mode. Note: This bit is only valid if Auto-Negotiation is enabled and com- plete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. 1 Speed Status 0, RO Speed10: This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced Modes. 1 = 10 Mb/s mode. 0 = 100 Mb/s mode. Note: This bit is only valid if Auto-Negotiation is enabled and com- plete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link. 0 Link Status 0, RO Link Status: This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be cleared upon a read of the PHYSTS regis- ter. 1 = Valid link established (for either 10 or 100 Mb/s operation) 0 = Link not established. Table 21. PHY Status Register (PHYSTS), address 0x10 (Continued) Bit Bit Name Default Description |
类似零件编号 - DP83848H |
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类似说明 - DP83848H |
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