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DP83848H 数据表(PDF) 40 Page - National Semiconductor (TI) |
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DP83848H 数据表(HTML) 40 Page - National Semiconductor (TI) |
40 / 78 page www.national.com 40 7.1.1 Basic Mode Control Register (BMCR) Table 12. Basic Mode Control Register (BMCR), address 0x00 Bit Bit Name Default Description 15 Reset 0, RW/SC Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. 14 Loopback 0, RW Loopback: 1 = Loopback enabled. 0 = Normal operation. The loopback function enables MII transmit data to be routed to the MII receive data path. Setting this bit may cause the descrambler to lose synchronization and produce a 500 µs “dead time” before any valid data will appear at the MII receive outputs. 13 Speed Selection RW Speed Select: When auto-negotiation is disabled writing to this bit allows the port speed to be selected. 1 = 100 Mb/s. 0 = 10 Mb/s. 12 Auto-Negotiation Enable RW Auto-Negotiation Enable: Strap controls initial value at reset. 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ig- nored when this bit is set. 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. 11 Power Down 0, RW Power Down: 1 = Power down. 0 = Normal operation. Setting this bit powers down the PHY. Only the register block is en- abled during a power down condition. 10 Isolate 0, RW Isolate: 1 = Isolates the Port from the MII with the exception of the serial man- agement. 0 = Normal operation. 9 Restart Auto- Negotiation 0, RW/SC Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation pro- cess. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0 = Normal operation. 8 Duplex Mode Strap, RW Duplex Mode: When auto-negotiation is disabled writing to this bit allows the port Du- plex capability to be selected. 1 = Full Duplex operation. 0 = Half Duplex operation. |
类似零件编号 - DP83848H |
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类似说明 - DP83848H |
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