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MC100ES6254ACR2 数据表(PDF) 6 Page - Integrated Device Technology |
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MC100ES6254ACR2 数据表(HTML) 6 Page - Integrated Device Technology |
6 / 9 page MC100ES6254/D 6 TIMING SOLUTIONS APPLICATIONS INFORMATION Example Configurations Understanding the junction temperature range of the MC100ES6254 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6254, the MC100ES6254 is specified, characterized and tested for the junction temperature range of TJ=0°C to +110°C. Because the exact thermal perfor- mance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific con- ditions to the published performance data of this data sheet. The correlation of the junction temperature range to the appli- cation ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja ⋅ Ptot Assuming a thermal resistance (junction to ambient) of 54.4 °C/W (2s2p board, 200 ft/min airflow, refer to table 4) and a typical power consumption of 467 mW (all outputs terminated 50 Ω to V TT, VCC=3.3 V, frequency independent), the junction temperature of the MC100ES6254 is approximately TA +24.5°C, and the minimum ambient temperature in this ex- ample case calculates to -24.5 °C (the maximum ambient tem- perature is 85.5 °C. Refer to Table 8). Exceeding the minimum junction temperature specification of the MC100ES6254 does not have a significant impact on the device functionality. How- ever, the continuous use the MC100ES6254 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Refer to the Applica- tion Note AN1545 for a power consumption calculation guide- line. a. The MC100ES6254 device function is guaranteed from TA=-40°C to TJ=110°C Maintaining Lowest Device Skew The MC100ES6254 guarantees low output-to-output bank skew of 50 ps and a part-to-part skew of maximum 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. SEL0 SEL1 Switch configuration 0 0 CLK0 clocks system A and system B 0 1 CLK1 clocks system A and system B 10 CLK0 clocks system A and CLK1 clocks system B 1 1 CLK1 clocks system B and CLK1 clocks system A CLK0 CLK1 SEL0 SEL1 System A System B MC100ES6254 3 3 2x2 clock switch CLK0 CLK1 SEL0 SEL1 MC100ES6254 0 1:6 Clock Fanout Buffer SEL0 SEL1 Switch configuration 0 0 System loopback 0 1 Line loopback 1 0 Transmit / Receive operation 1 1 System and line loopback CLK0 CLK1 SEL0 SEL1 Transmitter Receiver MC100ES6254 Loopback device QA[] System-Tx System-Rx 0 QB[] Table 8. Ambient temperature ranges (Ptot = 467 mW) Rthja (2s2p board) TA, minaTA, max Natural convection 59.0 °C/W -28 °C 82 °C 100 ft/min 54.4 °C/W -25 °C 85 °C 200 ft/min 52.5 °C/W -24.5 °C 85.5 °C 400 ft/min 50.4 °C/W -23.5 °C 86.5 °C 800 ft/min 47.8 °C/W -22 °C 88 °C Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com MC100ES6254 2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer NETCOM IDT™ 2.5/3.3V Differential LVPECL 2x2 Clock Switch and Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC100ES6254 6 |
类似零件编号 - MC100ES6254ACR2 |
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类似说明 - MC100ES6254ACR2 |
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