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S-1132B39-M5T1G Datasheet(数据表) 10 Page - Seiko Instruments Inc

部件型号  S-1132B39-M5T1G
说明  HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR
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制造商  SII [Seiko Instruments Inc]
网页  http://www.sii.co.jp
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HIGH RIPPLE-REJECTION LOW DROPOUT MIDDLE OUTPUT CURRENT CMOS VOLTAGE REGULATOR
S-1132 Series
Rev.3.2_00
10
Seiko Instruments Inc.
Standard Circuit
VSS
VOUT
ON/OFF
VIN
CIN
*1
CL
*2
INPUT
OUTPUT
GND
Single GND
*1. CIN is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 0.1
µF or more can be used for CL.
Figure 11
Caution
The above connection diagram and constant will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constant.
Application Conditions
Input capacitor (CIN):
0.1
µF or more
Output capacitor (CL):
0.1
µF or more
ESR of output capacitor:
2.0
Ω or less
Caution
A general series regulator may oscillate, depending on the external components selected. Check
that no oscillation occurs with the application using the above capacitor.
Selection of Input and Output Capacitors (CIN, CL)
The S-1132 Series requires an output capacitor between the VOUT and VSS pins for phase compensation. Operation is
stabilized by a ceramic capacitor with an output capacitance of 0.1
µF or more in the entire temperature range. However,
when using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, a ceramic capacitor with a capacitance
of 0.1
µF or more and an ESR of 2.0 Ω or less is required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output capacitor.
The required capacitance of the input capacitor differs depending on the application.
The recommended value for an application is 0.1
µF or more for CIN and 0.1 µF or more for CL; however, when selecting the
output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device.




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